Why no RDRAM-AMD mobo solutions?

[Kartman]

Hello All,

I am curious as to why we have not seen (or I have not seen) any marketed solutions that employ 800 MHz RDRAM memory on mobo designed for AMD XP/MP processors. I see people eagerly looking for 333 MHz DDR, which some call high-speed DDR, but surely the 800 MHz memory would be of greater breadth than 333 MHz, wouldn't it?

Also, the price point for 800 MHz DRRAM is less than 333 MHz DDR. I know I know little if anything about memory architectures and the business licensing issues therein, but hasn't anyone else wondered this, too? Instead, I am seeing posts about people overclocking PC2100, which will probably lead to someone (soon) asking about overclocking 2400 and 2700 DDR.

I do understand that Rambus' stupid business decisions early on cost them the market share, but at today's price points and the fluidity of mobo manufacturers to develop and deploy mobos to take advantage of even the smallest markets confuses me why this has not already happened.

 

[Elledan]

Any CPU but the P4 is incapable of dealing with the high-latency of RDRAM.

 

[Kartman]

Ok, then can someone explain the reason why ANYONE would use RDRAM with the P4? Or, is the current licensing allowances for DDR and Intel chipsets for P4 mobos simply going to kill Rambus 100%? I was under the impression that RDRAM provided the bandwidth not capable with SDRAM and only minimally capable with DDR.

I would like to think the RDRAM has/had the ability for memory bandwidth scaling that is needed for the P4 processor line since it is demands (more than AMD?). If RDRAM is so worthless why do people still make the memory, why do people make the mobos, why, why, why? hehe Please explain the latency as a comparitive frame of reference between RDRAM and DDR? I guess the speed/frequency is not a determining factor, because if it were I'd (naively) think RDRAM had something over DDR.

 

[atrowe]

<< Any CPU but the P4 is incapable of dealing with the high-latency of RDRAM. >>



The first P3s used RDRAM.

 

[Elledan]

<<

<< Any CPU but the P4 is incapable of dealing with the high-latency of RDRAM. >>



The first P3s used RDRAM. >>


They did? I don't think I've heard about this. Got any sources?

 

[Rand]

<<

<<

<< Any CPU but the P4 is incapable of dealing with the high-latency of RDRAM. >>



The first P3s used RDRAM. >>


They did? I don't think I've heard about this. Got any sources? >>



Intel I820 and I840 chipsets, single and dual channel RDRAM respectively. They were Intel's first official 133MHz FSB platforms for the P6 core architecture.

FWIW, AMD has a license to develop RDRAM chipsets for the Athlon if they so chose.
I can't say I think RDRAM would be a very good alternative to PC2100 DDR SDRAM on the Athlon at present as DDRSDRAM supplies enough bandwidth for the 266MHz FSB Athlons, without the added latency.

 

[Elledan]

Thank you, Rand

 

[MustPost]

Only problem was the 820 was slower than the 815.

 

[Rand]

<< Only problem was the 820 was slower than the 815. >>



Which wasnt exactly a problem given that the I815 was little more then a rumor when the I820 was introed. The I820's direct competitor and indeed, it's only real competition at the time was VIA's Apollo Pro 133A chipset.

 

[Shalmanese]

Becuase PCresources never got off his fat ass and developed it

 

[spazntwich1]

<< Becuase PCresources never got off his fat ass and developed it >>



I don't know how people are going to get that, but your that's hilarious.

 

[Elledan]

<< Becuase PCresources never got off his fat ass and developed it >>

What's the deal with Patrick anyway? What happened to him?

 

[ElFenix]

<< but surely the 800 MHz memory would be of greater breadth than 333 MHz, wouldn't it? >>


not when you're running 16 bit wide paths on the 800MHz vs 64 bit wide paths on the 333MHz. the better figure to compare is the bandwidth figure (which intel doesn't like to talk about for ddr, because that makes it sound faster) 1.6BGBps for 800MHz drdram vs 2.7GBps for 333MHz ddr sdram. intel gets about it with the p4 by offering a dual-channel drdram solution at 3.2GBps, combined with a matching bandwidth on the FSB for the p4. nvidia offers a dual-channel ddr sdram chipset for the athlon, offering 2 channels of pc2100 ddr for 4.2GBps of bandwidth. that doesn't help the athlon much since the athlon is still choking on 2.1GBps of FSB.

 

[Shalmanese]

<<

<< Becuase PCresources never got off his fat ass and developed it >>

What's the deal with Patrick anyway? What happened to him? >>



he "died" .

Anyway, I assumed the HT community would be more appreciative of the in joke that the general AT community.

 

[Elledan]

<<

<<

<< Becuase PCresources never got off his fat ass and developed it >>

What's the deal with Patrick anyway? What happened to him? >>



he "died" .

Anyway, I assumed the HT community would be more appreciative of the in joke that the general AT community. >>


?!?!

Notice: if your intention was to confuse me, your effort was most successful...

<---

 

[Rand]

<<

<< but surely the 800 MHz memory would be of greater breadth than 333 MHz, wouldn't it? >>


not when you're running 16 bit wide paths on the 800MHz vs 64 bit wide paths on the 333MHz. the better figure to compare is the bandwidth figure (which intel doesn't like to talk about for ddr, because that makes it sound faster) 1.6BGBps for 800MHz drdram vs 2.7GBps for 333MHz ddr sdram. intel gets about it with the p4 by offering a dual-channel drdram solution at 3.2GBps, combined with a matching bandwidth on the FSB for the p4. nvidia offers a dual-channel ddr sdram chipset for the athlon, offering 2 channels of pc2100 ddr for 4.2GBps of bandwidth. that doesn't help the athlon much since the athlon is still choking on 2.1GBps of FSB. >>




Partially due to the lower pin count RDRAM is dramatically easier to implement in a dual channel operationt though.

 

[spazntwich1]

<<

<<

<<

<< Becuase PCresources never got off his fat ass and developed it >>

What's the deal with Patrick anyway? What happened to him? >>



he "died" .

Anyway, I assumed the HT community would be more appreciative of the in joke that the general AT community. >>


?!?!

Notice: if your intention was to confuse me, your effort was most successful...

<--- >>



The person who was PCRecources claimed to be many different people. At one point, he stated that "his labs were working on a RDRAM + Athlon" chipset, platform solution, something. Basically, he sounded like a big BSer, and for some reason or other, he was banned.

Then, someone posted in offtopic claiming that PCResources had died helping people get out of the WTC on 9/11. It sounded like BS as well, and the mods banned the guy.

*shrug*. Nobody can REALLY know the whole deal with the dude, but most everyone assumes (as I do) that he was a total fake.

 

[Shalmanese]

Actually, a "friend" of his posted that he had died in afgansitan in military service. When a couple of people claimed that was BS and puleld holes in his story, the mods looked into it further and found out that his "fried" was actually him. According to him, he was a millionaire swedish special forces who ran a computer company in the US with no webpage and no contact details.

 

[Elledan]

<< Actually, a "friend" of his posted that he had died in afgansitan in military service. When a couple of people claimed that was BS and puleld holes in his story, the mods looked into it further and found out that his "fried" was actually him. According to him, he was a millionaire swedish special forces who ran a computer company in the US with no webpage and no contact details. >>


Sounds fishy enough to me Thanks for explaining!

 

[spazntwich1]

<< Actually, a "friend" of his posted that he had died in afgansitan in military service. When a couple of people claimed that was BS and puleld holes in his story, the mods looked into it further and found out that his "fried" was actually him. According to him, he was a millionaire swedish special forces who ran a computer company in the US with no webpage and no contact details. >>



Yeah, you're right. Sorry for the misinformation.

 

[AlastorX82]

REPOST!

 

[Degenerate]

Actually, has anyone been able to find out the results of putting more bandwidth into the P4?

 

[StandardCell]

<< Partially due to the lower pin count RDRAM is dramatically easier to implement in a dual channel operationt though. >>



No! RDRAM is very difficult to design with, and their applications support is some of the worst in the industry. One of my first projects was to assist in the design of an ball grid array package to handle three dual-channel 800MHz RDRAM interfaces for a network chip. The specifications for the packaging and I/O signal integrity requirements are quite specific. Each signal line must have at least one ground line next to it (which I still don't believe was adequate), and then the channel voltage reference had to be bounded on BOTH sides by a ground line. Much easier said than done when the on-chip RDRAM IP core had a fixed and very tightly packed pad layout on chip according to Rambus guidelines, yet the large package size with two bond finger tiers and crazy internal package traces made this a very very very VERY difficult and time consuming process. We spent the better part of five months getting the package finalized, hand-checking everything over and over again, and it ended up costing our customer an additional $70k just for the custom package substrate. The non-flip-chip packaging restrictions for DDR interfaces are not as bad because, while you have many more signals to route, the actual routing and grounding requirements aren't as strict as Rambus'.

We also had a problem with Rambus' support, trying to get them to tell us how far we needed to put an on-chip PLL to make sure that substrate noise didn't cause operational problems. No matter how many times we asked, their applications support basically ignored our requests for information. Eventually, we did away with it in the design, but we were not pleased, and it caused fairly significant design delays. With this much trouble, and with this kind of support and design constraints from Rambus, along with high licensing costs (DDR is essentially an open standard), it's no big surprise that there are not many manufacturers willing to pony up the design resources and support for a Rambus core.

 

[MadAd]

plus the cost on mobo manufacturers (and u the customer) making a 7 layer pcb to house all the tracks for RD, instead of the 3-4 layer ones of today