Anarchist420
Diamond Member
What does intel do that gives their CPUs more performance per clock?
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Why is intel faster per core?
- Thread starter Anarchist420
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MJinZ
Diamond Member
ModestGamer
Banned
If only the topic was as simple as aerodynamics and horsepower
Phynaz
Lifer
There is nothing "simple" about the performance of chips OR cars.
ModestGamer
Banned
DominionSeraph
Diamond Member
Yup. Give a redneck a Honda Civic and $15,000 and he'll get it to go faster than a Lamborghini and have it doing it in a 1/4 mile to boot.
MrK6
Diamond Member
ModestGamer
Banned
Intel I7 cores are a LOT bigger than AMD Phenom II cores. They have a lot more logic in their cores, so having a higher IPC is really expected. If they didn't then I would really start to wonder. (An I7 core is about 2x as big as an Phenom II core if I recall correctly. I'll have to go back and find the dimensions again to check.)
kinda like why i could never jump as high as Micheal jordan.
I mean even the nike comericals says its gotta be the shoes..
LuLz.. and here comes a person in a Suzuki Hayabusa going WTF are you doing red neck...
Get a bike noob!
conroe had a big wide execution unit. nahelem feeds that big wide execution unit better. sandybridge seems to be that same execution unit with more of everything.
in car terms it'd be like going from a V8 with a carb, to the same block with EFI, to the same block with DI. same internals but the stuff around it keeps the internals working at a higher %.
K10/10.5 is very similar in design to conroe/nehalem. K8 is fairly similar but of course didn't have the cache structure and some of the other advanced outer bits (K10 is heavily based on K8).
it looks like bulldozer will be the first big change in how the execution units are designed since the pentium 4 debuted (as conroe is really a throwback to the design philosophy of the pentium pro/2/3)
for background:
http://www.anandtech.com/show/1998
in car terms it'd be like going from a V8 with a carb, to the same block with EFI, to the same block with DI. same internals but the stuff around it keeps the internals working at a higher %.
K10/10.5 is very similar in design to conroe/nehalem. K8 is fairly similar but of course didn't have the cache structure and some of the other advanced outer bits (K10 is heavily based on K8).
it looks like bulldozer will be the first big change in how the execution units are designed since the pentium 4 debuted (as conroe is really a throwback to the design philosophy of the pentium pro/2/3)
for background:
http://www.anandtech.com/show/1998
Last edited:
edplayer
Platinum Member
except there is no way that you can get a Civic to be faster than a Lamborghini within a 1/4 mile for $15,000 or less
unless you are talking about a very old Lamborghini
Like the way a six core i7 980X monster is 240mm^2 while a phenom II X4 is a svelte 258mm^2 ? 😉
Even if we're talking bloomfield, they are about the same size and the Intel chip has fewer transistors than the Phenom II X4.
edit: sources - http://www.anandtech.com/show/2960
Last edited:
Scotteq
Diamond Member
WOAH!!! 😱
Rednecks have Fabs!?!??! D: 😱 D: 😱 D: 😱
Well... I guess that *does* explain the duct tape on my southbridge. :hmm:
**
Oh: Give me the $15K: I'll buy a sportbike that'll smoke both of those, *and* have enough left over for a new build. 😉
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Look at the transistor count and die area of the actual cores. You will see what I am talking about. Phenom 2's have a much larger Cache area than Intel, and much smaller core area per die.
http://www.3dnow.net/phpBB2/viewtopic.php?f=1&t=1471&view=previous
Nehalem Core Size = 24.4mm^2
Shanghai Core Size = 15.3mm^2
Also, the Nehalem has 731M Transistors, and the Shanghai has 705M Transistors. So no, the I7 does not have fewer transistors.
Also, you are comparing 32nm to 45nm for some reason. That has nothing to do with the question of IPC, but more the manufacturing process.
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evolucion8
Platinum Member
But the Intel i7 980X is using the 32nm process while the Phenom II X4 is using the 45nm process.
Gamingphreek
Lifer
Since nobody on here seems to want to answer the questions seriously, I'll give a brief overview of some basic processor architecture.
Before I start; however, the die size as *NOTHING* to do with the speed of the chip.
First off, you need to understand the very basics of an Instruction Pipeline. For an EXTREMELY basic architecture (Even moreso than MIPS) you have a pipeline that resembles this:
Fetch, Decode, Execute, Store
As an instruction, take ADD for instance, is fed through the pipeline, it goes through each of these steps.
Now the longer the pipeline, the higher the clockspeed must be in order to achieve the same number of instructions per clock (IPC). Intel, in going back to the Pentium Pro architecture starting with the Centrino Platform, allowed for a much higher instruction per clock at a lower clockspeed. The Core, Core 2, and subsequent iterations are based off of this architecture.
Without getting too much more in-depth, although neither manufacturer has released the instruction pipeline length, one would think that Intel's pipeline was shorter.
-----------------
On a different note, Intel has always had excellent branch prediction logic.
To understand branch prediction, you have to understand the concept of pipelining. If you are interested in this sort of topic, I suggest reading more about it, but for the sake of keeping this post short, pipelining is essentially feeding as many instructions as possible to keep every stage of the prior mentioned instruction pipeline populated. In other words, we don't want an add to pass the FETCH stage and then nothing happen on the FETCH stage until the ADD has completely written to memory.
Consider the basic piece of assembly code (Note: it is completely useless and does literally nothing but show the value of branch prediction):
push %ebp
movl %ebp, %esp
subl %esp, 4
addl %eax, %edx
cmpe %eax, %edx
jne .CODE_1
addl %eax, %edx
mul %eax, 2
With the concept of pipelining in mind, you can see that the JNE (Jump Not Equal) will go through the instruction pipeline, but so will the ADDL and MUL instructions. What if the JNE actually tests to true though and the program has to jump to a new segment of code. The ADDL and MUL instructions are invalid and must be flushed from the pipeline thereby using up precious clock cycles. We call this a branch misprediction. Having to fill the instruction pipeline with NOP's to flush it before continuing is a costly mistake.
With that in mind, a branch prediction unit will attempt to determine (Based on any number of variables depending on whether it is static or dynamic) whether or not to take the JNE or to load instructions on the assumption that it fails.
-------------
So now we have 2 reasons which could lead to Intel being fast on a clock-clock basis. While there are numerous reasons why this could be the case (Cache policy, cache size, Hyperthreading, OPS Fusion, Compiler Optimization, etc...) hopefully this gives you an extremely small sample of Microprocessor Architecture and an answer to your question.
-Kevin
Before I start; however, the die size as *NOTHING* to do with the speed of the chip.
First off, you need to understand the very basics of an Instruction Pipeline. For an EXTREMELY basic architecture (Even moreso than MIPS) you have a pipeline that resembles this:
Fetch, Decode, Execute, Store
As an instruction, take ADD for instance, is fed through the pipeline, it goes through each of these steps.
Now the longer the pipeline, the higher the clockspeed must be in order to achieve the same number of instructions per clock (IPC). Intel, in going back to the Pentium Pro architecture starting with the Centrino Platform, allowed for a much higher instruction per clock at a lower clockspeed. The Core, Core 2, and subsequent iterations are based off of this architecture.
Without getting too much more in-depth, although neither manufacturer has released the instruction pipeline length, one would think that Intel's pipeline was shorter.
-----------------
On a different note, Intel has always had excellent branch prediction logic.
To understand branch prediction, you have to understand the concept of pipelining. If you are interested in this sort of topic, I suggest reading more about it, but for the sake of keeping this post short, pipelining is essentially feeding as many instructions as possible to keep every stage of the prior mentioned instruction pipeline populated. In other words, we don't want an add to pass the FETCH stage and then nothing happen on the FETCH stage until the ADD has completely written to memory.
Consider the basic piece of assembly code (Note: it is completely useless and does literally nothing but show the value of branch prediction):
push %ebp
movl %ebp, %esp
subl %esp, 4
addl %eax, %edx
cmpe %eax, %edx
jne .CODE_1
addl %eax, %edx
mul %eax, 2
With the concept of pipelining in mind, you can see that the JNE (Jump Not Equal) will go through the instruction pipeline, but so will the ADDL and MUL instructions. What if the JNE actually tests to true though and the program has to jump to a new segment of code. The ADDL and MUL instructions are invalid and must be flushed from the pipeline thereby using up precious clock cycles. We call this a branch misprediction. Having to fill the instruction pipeline with NOP's to flush it before continuing is a costly mistake.
With that in mind, a branch prediction unit will attempt to determine (Based on any number of variables depending on whether it is static or dynamic) whether or not to take the JNE or to load instructions on the assumption that it fails.
-------------
So now we have 2 reasons which could lead to Intel being fast on a clock-clock basis. While there are numerous reasons why this could be the case (Cache policy, cache size, Hyperthreading, OPS Fusion, Compiler Optimization, etc...) hopefully this gives you an extremely small sample of Microprocessor Architecture and an answer to your question.
-Kevin
:O so your saying because intel is blue, amd being green, and blue > Green, thats not a serious answer?
:O
Blue is a primary color Dammit!!
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