Why Intel 14nm was named ...14nm?

[wingman04]

Well, at 10nm the most important thing they could do are:

• Put fins (and interconnect wires and gates) even closer together (for about 2x more transistors/mm²)
• Make gate even shorter
• Put III-V and Ge in the channel for higher performance (mobility) and (potentially vastly improved?) lower power
• Improve the fin with a quantum well, which will result in 3 sides being controlled by gate + the 4th side isolated

We'll just have to see what they have done. It's been a long time since 14nm+10nm density plans were disclosed (3 years now) and 2 years since 14nm transistor briefing, and it will still be another year until the new transistor gets released 🙁.

Do you think there will be Quantum tunnelling at 5nm?

 

[witeken]

Do you think there will be Quantum tunnelling at 5nm?

There's already quantum tunneling, at some parts of the transistor more than others.

Since 45nm (or 28 TSMC), HKMG is used to reduce leakage by I think maybe 100x. It was some ridiculous high number. At 22nm (16nm others) FinFET were introduced and they also reduced leakage a lot. Leakage is for a big part (maybe all?) because of quantum tunneling: it only became a problem from the ~130-90nm node onward. It suddenly grew by many order of magnitudes in a few nodes and so from being negligible it became a meaningful % of power consumed.

This was especially because the gate dioxide (barrier between channel and gate) was getting only 1nm big, that's why HKMG was such a big deal.

 

[ninaholic37]

wingman04 are you really posting from a Pentium III? My laptop is a Pentium M.

 

[wingman04]

wingman04 are you really posting from a Pentium III? My laptop is a Pentium M.

No the Pentium III was my favorite it was the biggest jump in processing power. I'm posting from i5 6600k, OC 4.5GHz, hyper 212, Gigabyte Z170 HD3, EVGA SSC GTX 970.

How do you like your Pentium M on the internet?

 

[t1gran]

Yes, Intel's 2014 presentation at the International Electron Devices Meeting (IEDM): http://www.intel.com/content/dam/ww...foundry/intel-14nm-iedm-2014-presentation.pdf.

Hi! Don't you know if there is similar document about 10nm? Details were announced yesterday, but I found no information about gate length in 10nm manufacturing process. I also wonder how to get access to manufacturing process specs from the head page of Intel's website.

 

[witeken]

Hi! Don't you know if there is similar document about 10nm? Details were announced yesterday, but I found no information about gate length in 10nm manufacturing process. I also wonder how to get access to manufacturing process specs from the head page of Intel's website.

No, Intel has not disclosed gate length. They might do a 10nm presentation at IEDM 2017 in December, that would be a logical thing to do.

 

[beginner99]

Although I wonder how much of an impact it actually has. Intel increased fin height from 32nm to 42nm and TSMC/Samsung are in between those 2 values. And it isn't like 14nm overclocks dramatically better than 22nm.

Plus given that Ryzen beats 6900k at performance/watt (and pure performance) in highly threaded loads. So either intel 14 nm isn't that good or Ryzen is a superior uArch.

 

[thepaleobiker]

This has been a fantastic thread to read/learn from. Thanks! Will keep reading! (and also over at semiaccurate)

Regards,
Vish

 

[oak8292]

There is a lot of new information from Intel with their manufacturing day presentations. A easy set of links to follow are provided on SemiWiki by D Nenni.

https://www.semiwiki.com/forum/f293/intels-manufacturing-day-materials-9145.html

There is also a commentary by Scotten Jones on SemiWiki on the node names and Bohr's proposal to change the metric for naming nodes.

https://www.semiwiki.com/forum/cont...-day-nodes-must-die-but-moores-law-lives.html

Intel is claiming a three year lead, however it isn't a full node as the density lead is only 30%.

The most intriguing presentation is Mark Bohr's on the new Intel 22FFL process. Intel tightened up on the fin pitch and relaxed the gate and metal pitch to increase density with drive currents similar to their own 14nm ++. Who will get access and why did they develop the process?

 

[thepaleobiker]

There is a lot of new information from Intel with their manufacturing day presentations. A easy set of links to follow are provided on SemiWiki by D Nenni.

https://www.semiwiki.com/forum/f293/intels-manufacturing-day-materials-9145.html

There is also a commentary by Scotten Jones on SemiWiki on the node names and Bohr's proposal to change the metric for naming nodes.

https://www.semiwiki.com/forum/cont...-day-nodes-must-die-but-moores-law-lives.html

Intel is claiming a three year lead, however it isn't a full node as the density lead is only 30%.

The most intriguing presentation is Mark Bohr's on the new Intel 22FFL process. Intel tightened up on the fin pitch and relaxed the gate and metal pitch to increase density with drive currents similar to their own 14nm ++. Who will get access and why did they develop the process?

D Nenni has tons of good info/articles on semiwiki! 🙂 I saw his post the other day. Brutal on Intel though.

 

[Borealis7]

In brief, this index is smaller, which mean that, you have stronger chip with less amount of electricity consumed

BUT...smaller chip die (less area) * more transistors = more heat density which is BAD. couple that with Intel's bad TIM and micro-gap between die and IHS and you get blazing load temps ever since Ivy Bridge.