Elite Member, Moderator Emeritus
- Oct 9, 1999
Originally posted by: imgod2u
Not really. As I stated in a previous post, the SSE/SSE2 component of the P4 is 128-bit. It has a register buffer that is able to contain clusters of data (multiple FP or Integer data that combine to 128-bit) and schedule it for execution. The G4's AltiVec component is actually very similar to that of the P4. The reason the G4 is good in distributed computing, especially RC5 is due to its RISC-like nature. Without the limitations of x86 such as only 3 instruction decodes per clock and a massive integer execution engine, it can achieve much better results when performing pure integer math.
The P4 and the G4 aren't nesssarily in the same league. While you're right to the most part(especially why the P4 does indeed do poorly), the P4's SSE 128-bit powers aren't the same. I don't have the exact reason on hand, but Distributed.net's client development team said that they can't go about using the P4 the same way they can the G4 due to the registers in question. In this case, I believe it was the lack of registers on the P4(PPC chips have more registers, especially of the nice 128bit general purpose variety). Either way, excuse my rambling. Whenever someone mentions the G4 and 128-bits, I get long winded. It's not a killer CPU without a clockspeed boost, but there are some cases where its design can make it far faster than any current x86 design.