I'm gonna have to pick at this one.
Originally posted by: busmaster11
I've noticed that AMD has generally preferred the more conservative route. While Intel goes for brute force architectures that enable higher clock speed, ie P4 / RDRAM, AMD has gone for more intelligent, yet evolutionary designs.
SDRAM is far from revolutionary. DDR technology was in RDRAM long before it was in DDR SDRAM.
AMD's K7 design is merely a brute force way of shoving more execution units in a chip based on an old 10-stage design with very little life left (well, at the initial K7 launch, it had some life left but we're seeing it reach its end now). Think Pentium 3 (P6 core) with a few more execution units and fetch capabilities and you get the K7. It's a great short-term, uber-performance per clock design, but in no way revolutionary or even innovative.
The P7 core is a high-scalable design that will last years. The P4 is a hacked-down, compromised design that relies on brute clockspeed to gain speed advantages and make up for its lack of fetch abilities and FP power. Same concept of stressing one feature to make up for the shortcommings of another part of the design.
All things being equal, increasing performance through higher clock speeds will generate instability more often than increasing performnce by making a more intelligent chip, which is what AMD has done. While DDR and QDR, if and when it arrives, will always be able to trace its roots back to SDRAM, RDRAM is more revolutionary. But its key negative, that it does so little per clock cycle, bugs me. That plus the fact that its been years since its introduction, and its prices are still double that of DDR.
Work per cycle is nothing more than a design concept. It's relation to efficiency, or "intelligence" as you call it is the same as clockspeed's relation to performance. In other words, it has none. The market is moving towards narrow-band, high per-pin frequency designs. Would you say Hypertransport "bugged" you because it is only 8-bits wide? It's simply a different route and currently, it's the better route.
Intel has seen it, and its no coincidence that they immediately surfaced with i845DDR immediately after their contract with rambust expired. I hope the bastards at rambust are forced to pay back every penny they conned out of the Jedec organizations.
RDRAM had a lot of potential. However, I think even Intel was a bit frightened by Rambus's boldness. If you ask me, they had a sweet deal with Intel. They really didn't need to pull all of that crap. But hey, Granite Bay's looking great.
the Athlon IS as bandwidth hungry as the P4. that explains why you see increases in performance as the fsb and RAM increase in speed.
http://www.anandtech.com/cpu/showdoc.html?i=1595&p=12 seems to indicate differently.
The Athlon is not memory-starved, not at 1.67ish GHz anyway. Memory bandwidth requirements are directly releated to how many instructions are fetched per second and how many instructions the CPU works on at any given time. For the Athlon, that's 10 integer instructions at any given time (once the integer pipeline is filled up) and x86's fundamental limitation of 3 instruction fetches per clock. At 1.67 GHz, that's not a lot of strain on the memory bandwidth.
The P4 fetches 3 x86 instructions per cycle as well and works on 20 integer instructions at any given time (assuming the pipeline is filled). At 2.0 GHz or 2.2 GHz, that's a big strain on memory. So in other words, it is much more memory starved.