When will AMD's Shanghai CPU come to market?

[Nemesis 1]

Originally posted by: Viditor

Originally posted by: dmens

Originally posted by: Viditor
They also said that the screwups on the 65nm Barcelonas have saved them from having any problems on the 45nm Barcelonas (they're almost the same design). They are experiencing record yields on 45nm test runs, and will begin production runs at fully mature yields.

Design problems on 65nm barcelonas somehow fixed yields on 45nm shrinks? Epic lulz.

Ummm...that's not what I said.
Using numbers, and explaining in much more detail for you:

1. Design problems on 65nm Barcelona have allowed AMD to produce 45nm Shanghai without design problems...so no delays will incure as they did with AMD's first attempt at this architecture.

2. In addition to that, they are experiencing record yields so volume production means volume production and they will begin at mature yields.

Interesting . Please a link to AMDs record mature yields at 45nm. I really don't believe this . Any person that has any reasoning abilities would also have doubts about those facts.

When did AMD fix there 65nm process. You know . Why does amd cpu's use more energy than intels 65nm process. This problem isn't going away at 45nm like you seem to believe . dies made with SOI the smaller process its on leaks even further. PROOF THAT amd has solved this problem because they haven't on 65nm.

I have watched you post this stuff for over 2 years . Now I may be wrong here , not sure . But in 2 years you haven't gotten anything right . About AMD not 1 thing.

I understand you like AMD but stop making things up and for cring out loud stop believeing AMD hype. Because thats all it is .

When 45nm. k10 appears with its minor improvements intel will have Nehalem to fight 45nm AMD . at the server and highend . Penryn will take care of the low end.

Thats all true if you believe Intels hype. Right now at this moment in time Intel is 100% more believable that AMD. Every qt. AMD comes out with yet another lie. Just like the analyist that said AMD meet lowered 1st exspectations . Pure BS . I can prove it also . Guidance for AMDs 1st qt. Was lowered only after AMD lowered guidance for the qt.
These people have hyped amd now for 2 years . So many have lost creditability because of amd its got a lot of people thinking.

 

[Idontcare]

Originally posted by: Viditor
1. Design problems on 65nm Barcelona have allowed AMD to produce 45nm Shanghai without design problems...so no delays will incure as they did with AMD's first attempt at this architecture.

I don't disagree with this comment as this can be true for any chip-shrink so long as it is quite literally a "dumb shrink".

So what concerns me here when I see this kind of comment coming from AMD (I believe you, not going to check the CC for myself) is that it really implies AMD has changed little of the K10 design for Shanghai/Deneb.

Obviously they are basing their confidence behind this statement on the expectation that what little bits of the design has been changed have apparantely not been changed so aggressively as to jeopardize the likelihood of introducing a critical bug again.

Little change, and/or non-aggressively changed design, does not bode well for lofty expectations of substantial IPC improvements.

Originally posted by: Viditor
2. In addition to that, they are experiencing record yields so volume production means volume production and they will begin at mature yields.

This is more proof of what they already told the public - that their 45nm contains no new materials for integration (same old low-k dielectric in BEOL, same old SiON gate oxide, same old doped polysilicon gates, etc)...such that this "dumb" process shrink is giving them little issues in the way of ramping up yields.

So to sum up - it would appear to my educated eye that AMD is aiming Shanghai design and 45nm process node as being a slight bit impovement over Barcelona and 65nm process.

I don't expect anything more IPC-wise from Shanghai over Barcelona as we saw from Penryn over Conroe. (both bumped up the cache, added a few extra features, and called it a day)

And clockspeed and/or power reduction-wise I don't expect anything near what Intel did with 45nm over 65nm. (without new materials, about the only way AMD can reduce power consumption/leakage is by reducing Vcore at same GHz)

In conclusion - bummer

 

[Extelleron]

Originally posted by: Nemesis 1

Originally posted by: Viditor

Originally posted by: dmens

Originally posted by: Viditor
They also said that the screwups on the 65nm Barcelonas have saved them from having any problems on the 45nm Barcelonas (they're almost the same design). They are experiencing record yields on 45nm test runs, and will begin production runs at fully mature yields.

Design problems on 65nm barcelonas somehow fixed yields on 45nm shrinks? Epic lulz.

Ummm...that's not what I said.
Using numbers, and explaining in much more detail for you:

1. Design problems on 65nm Barcelona have allowed AMD to produce 45nm Shanghai without design problems...so no delays will incure as they did with AMD's first attempt at this architecture.

2. In addition to that, they are experiencing record yields so volume production means volume production and they will begin at mature yields.

Interesting . Please a link to AMDs record mature yields at 45nm. I really don't believe this . Any person that has any reasoning abilities would also have doubts about those facts.

When did AMD fix there 65nm process. You know . Why does amd cpu's use more energy than intels 65nm process. This problem isn't going away at 45nm like you seem to believe . dies made with SOI the smaller process its on leaks even further. PROOF THAT amd has solved this problem because they haven't on 65nm.

I have watched you post this stuff for over 2 years . Now I may be wrong here , not sure . But in 2 years you haven't gotten anything right . About AMD not 1 thing.

I understand you like AMD but stop making things up and for cring out loud stop believeing AMD hype. Because thats all it is .

When 45nm. k10 appears with its minor improvements intel will have Nehalem to fight 45nm AMD . at the server and highend . Penryn will take care of the low end.

Thats all true if you believe Intels hype. Right now at this moment in time Intel is 100% more believable that AMD. Every qt. AMD comes out with yet another lie. Just like the analyist that said AMD meet lowered 1st exspectations . Pure BS . I can prove it also . Guidance for AMDs 1st qt. Was lowered only after AMD lowered guidance for the qt.
These people have hyped amd now for 2 years . So many have lost creditability because of amd its got a lot of people thinking.

What Viditor is trying to say is that AMD is following their own version of Intel's tick-tock strategy, which AMD calles "Pipe."

The point of "Pipe" is that AMD will begin production of products on a new silicon process using an established CPU design. Since its tape out in Q4 2006, AMD has ironed out the problems with the Barcelona architecture and if you look at the B3 chips, they are looking quite good. With AMD's transition to Shanghai, they will only have to iron out the problems related to the new 45nm process and will not have to worry about problems arising from an immature architecture as well.

It's exactly what Intel is doing with tick-tock, only problem is AMD is a whole year behind.

AMD's Pipe:

First 65nm: Brisbane, established architecture on new process
Second 65nm: Barcelona, new architecture on established process
First 45nm: Shanghai, established architecture on new process
Second 45nm: Bulldozer, new architecture on established process

And so on.

Originally posted by: Idontcare

Originally posted by: Viditor
1. Design problems on 65nm Barcelona have allowed AMD to produce 45nm Shanghai without design problems...so no delays will incure as they did with AMD's first attempt at this architecture.

I don't disagree with this comment as this can be true for any chip-shrink so long as it is quite literally a "dumb shrink".

So what concerns me here when I see this kind of comment coming from AMD (I believe you, not going to check the CC for myself) is that it really implies AMD has changed little of the K10 design for Shanghai/Deneb.

Obviously they are basing their confidence behind this statement on the expectation that what little bits of the design has been changed have apparantely not been changed so aggressively as to jeopardize the likelihood of introducing a critical bug again.

Little change, and/or non-aggressively changed design, does not bode well for lofty expectations of substantial IPC improvements.

Originally posted by: Viditor
2. In addition to that, they are experiencing record yields so volume production means volume production and they will begin at mature yields.

This is more proof of what they already told the public - that their 45nm contains no new materials for integration (same old low-k dielectric in BEOL, same old SiON gate oxide, same old doped polysilicon gates, etc)...such that this "dumb" process shrink is giving them little issues in the way of ramping up yields.

So to sum up - it would appear to my educated eye that AMD is aiming Shanghai design and 45nm process node as being a slight bit impovement over Barcelona and 65nm process.

I don't expect anything more IPC-wise from Shanghai over Barcelona as we saw from Penryn over Conroe. (both bumped up the cache, added a few extra features, and called it a day)

And clockspeed and/or power reduction-wise I don't expect anything near what Intel did with 45nm over 65nm. (without new materials, about the only way AMD can reduce power consumption/leakage is by reducing Vcore at same GHz)

In conclusion - bummer

Certainly AMD isn't doing anything aggressive with design changes going from 65nm->45nm. They are tripling the size of the L3 cache and making slight improvements to the core.

As for the 15% figure... we'll have to see, I don't think it is entirely unrealistic but it is pretty substantial for what is mostly a die shrink. Taking things into perspective, Barcelona itself only offers about a ~20% improvement over K8 in most situations.

AMD's 45nm process isn't going to be some kind of miracle, they are going to trail Intel in performance like usual. The big question is how the lack of the high-k dielectric/metal electrode on 45nm will affect performance. Certainly there is a need for change in materials, but is it really necessary @ 45nm or is Intel blowing it out of proportion?

For AMD's second gen 45nm parts (Bulldozer I suppose) they still say they will be going 45nm high-k, I don't know if that is going to be true. Considering the IBM alliance seems focused on high-k for 32nm, I don't think AMD is going to develop a 45nm high-k process by itself.

 

[Idontcare]

Originally posted by: Nemesis 1
Interesting . Please a link to AMDs record mature yields at 45nm. I really don't believe this . Any person that has any reasoning abilities would also have doubts about those facts.

When you consider they are basically 1 year behind Intel's timeline for rolling out 45nm, in addition to the fact the process technologies are not aggressive by any standards for 45nm (no ultra low-k BEOL dielectric, no metal gates, no hi-k gate oxide) it really isn't surprising to believe that AMD is observing good yields on this relatively minor technology node improvement.

Everything about AMD's 45nm node so far is about cost reduction rather than performance improvements.

Immersion litho is a cost reduction technology, double-patterning like Intel does still results in the same critical dimensions as immersion-litho generates but it comes with higher cost (double patterning that is) because of the inherently longer cycle-times that the wafers spend in the fab.

The shrink will produce die-sizes that are smaller, easier to yield and so on. All good for cost reduction but not necessarily made of the stuff that generates higher performance (clockspeed wise or power reduction wise)

Originally posted by: Nemesis 1
When did AMD fix there 65nm process. You know . Why does amd cpu's use more energy than intels 65nm process. This problem isn't going away at 45nm like you seem to believe . dies made with SOI the smaller process its on leaks even further. PROOF THAT amd has solved this problem because they haven't on 65nm.

We can't really say whether AMD's 65nm process is "broken" any more than we could ever really say Intel's 90nm process was "broken". The problem with Prescott was certainly design related (intentional though) and not so much process related as Dothan turned out just fine on 90nm.

The metrics we need to assess how inferior or superior AMD's 65nm is to Intel's 65nm include their internal stats on Ion/Ioff plots, line-to-line leakage, IDDQ, gate leakage, as well as capacitance stats.

Both companies have this info, obviously as the designers need the info to be effective in their jobs, but it is rarely published in a form which enables apples-to-apples comparisons.

IEDM is the typical public forum where this info is published and discussed. Here's a nice article on RWT discussing last year's IEDM: http://www.realworldtech.com/p...icleID=RWT011608222300

If you look at the second to the last page on the RWT you will want to compare IBM to Intel for High-Performance 45nm. For example NMOS Ion for IBM is 1240mA while Intel is nearly 10% stronger at 1360mA. Ioff (a metric of idle leakage) for IBM is 200nA while Intel is 50% less at 100nA.

The performance discrepancy with PMOS is even more dire (in Intel's favor) thanks to Hik/MG...IBM Ion is 840mA while Intel is 27% stronger at 1070mA. Again the Ioff is 2X difference with IBM at 200nA and Intel at 100nA.

We don't have the info in this table to compare 65nm across both IBM (AMD) and Intel...but you can see where this is going. IBM's 45nm is not "broken" and I doubt their 65nm is broken either...but the chef's (chip designers) can only bake with the ingredients that are in their pantry and right now the AMD chef's pantry is looking quite bare compared to the pantry of Intel's chefs for 45nm.

And I'll just keep reiterating that this is what having 4X the R&D budget entitles you to have...if you throw 4X the money at buying spices for your kitchen then you sure as hell had better bake the best cake or pie the world has ever tasted. If you don't then you screwed over your shareholders and spent way more money on R&D than you should have.

 

[Kuzi]

Originally posted by: Nemesis 1
When did AMD fix there 65nm process. You know . Why does amd cpu's use more energy than intels 65nm process. This problem isn't going away at 45nm like you seem to believe . dies made with SOI the smaller process its on leaks even further. PROOF THAT amd has solved this problem because they haven't on 65nm.

You have things mixed up. AMD's 65nm process is not that good because they didn't/couldn't spend much time improving it. That's why even before Barcelona was released, Athlon X2 at 90nm maxed at 3.2GHz, while Athlon X2 Brisbane (65nm) only maxed at 2.7GHz.

K10 delays had nothing to do with 90nm, 65nm or 45nm processes, AMD had major problems/bugs with the native quad core design+IMC, and now the B3 revision seems to have ironed out all these problems. I think that is what Viditor meant.

Originally posted by: Idontcare
So to sum up - it would appear to my educated eye that AMD is aiming Shanghai design and 45nm process node as being a slight bit impovement over Barcelona and 65nm process.

I don't expect anything more IPC-wise from Shanghai over Barcelona as we saw from Penryn over Conroe. (both bumped up the cache, added a few extra features, and called it a day)

And clockspeed and/or power reduction-wise I don't expect anything near what Intel did with 45nm over 65nm. (without new materials, about the only way AMD can reduce power consumption/leakage is by reducing Vcore at same GHz)

In conclusion - bummer

Yes Shanghai will be a slight improvment over Barcelona, but the gain will be higher than what Penryn got over Conroe (6-7%). Conroe was already fast and had the correct cache hierarchy for the design.

On the other hand, Barcelona is handicapped the way it is now, the cache hierarchy is less than optimal. The L3 cache is too small for a quad core design, and it's running at a low clock speed causing higher latencies for the memory subsystem.

If AMD can get the CPU/IMC running at 1/1 speeds, a 15% clock-per-clock gain over Barcelona is very possible, and for some multithreaded applications that like large caches the gain could be even higher.

Power consumption will not be as good as Intel 45nm cpus, at least not with the first batch of Shanghai/Deneb cpus. But next year I'm sure AMD will lower the power draw on later revisions of 45nm cpus.

 

[dmens]

Originally posted by: Viditor
Ummm...that's not what I said.
Using numbers, and explaining in much more detail for you:

No need to explain, I know what you are implying. It's still hilariously delusional.

1. Design problems on 65nm Barcelona have allowed AMD to produce 45nm Shanghai without design problems...so no delays will incure as they did with AMD's first attempt at this architecture.

Yeah, no design problems from a new process. HAHAHA. Maybe in some kind of EE happyland. Even with a dumb shrink that is an absurd claim.

2. In addition to that, they are experiencing record yields so volume production means volume production and they will begin at mature yields.

OH RLY? OK fine, very few people even within AMD has hard numbers on this, but do you really think a new process can "start" at "mature yields"? See point above w.r.t. happyland.

 

[Viditor]

Originally posted by: dmens

Originally posted by: Viditor
Ummm...that's not what I said.
Using numbers, and explaining in much more detail for you:

No need to explain, I know what you are implying. It's still hilariously delusional.

1. Design problems on 65nm Barcelona have allowed AMD to produce 45nm Shanghai without design problems...so no delays will incure as they did with AMD's first attempt at this architecture.

Yeah, no design problems from a new process. HAHAHA. Maybe in some kind of EE happyland. Even with a dumb shrink that is an absurd claim.

2. In addition to that, they are experiencing record yields so volume production means volume production and they will begin at mature yields.

OH RLY? OK fine, very few people even within AMD has hard numbers on this, but do you really think a new process can "start" at "mature yields"? See point above w.r.t. happyland.

Whatever you say dmens...keep in mind that these weren't MY words, they're from the CC:

Robert J Rivet

..."Our world-class manufacturing facility in Dresden continues to set benchmarks for operating performance, including yields and cycle types. We continue to execute our 45-nanometer strategy according to plan and we will start production at mature yields this summer"

 

[Phynaz]

What your friend Bob said is they will have mature yields this summer, not that they have them now.

Also notice he never said what a mature yield is for AMD.

As far as record yields on test runs, well of course. It's been something like a year that they have been doing test runs right? I would expect that after a year of refinement yeilds will be better.

Notice though that no one is claiming record yields overall, just record yields on 45nm.

What is not said often tells a more complete story than what is said.

 

[bryanW1995]

it's just depressing to read about amd's troubles right now. We all need to buy up these cheap Q6600's while we can, I have a feeling that when nehalem rolls around we won't see great chips like these at this kind of price

 

[dmens]

Originally posted by: Viditor
Whatever you say dmens...keep in mind that these weren't MY words, they're from the CC:

Robert J Rivet

..."Our world-class manufacturing facility in Dresden continues to set benchmarks for operating performance, including yields and cycle types. We continue to execute our 45-nanometer strategy according to plan and we will start production at mature yields this summer"

so you simply regurgitate the PR lines from AMD? sure you are not a volunteer viral marketer?

 

[Viditor]

Originally posted by: dmens

Originally posted by: Viditor
Whatever you say dmens...keep in mind that these weren't MY words, they're from the CC:

Robert J Rivet

..."Our world-class manufacturing facility in Dresden continues to set benchmarks for operating performance, including yields and cycle types. We continue to execute our 45-nanometer strategy according to plan and we will start production at mature yields this summer"

so you simply regurgitate the PR lines from AMD? sure you are not a volunteer viral marketer?

It wasn't a PR, it was the CC...statements made in the CC are made under threat of penalties, PRs are not.

But I'm sure you understand AMD's business MUCH better than anyone in the company...

 

[dmens]

Originally posted by: Viditor
It wasn't a PR, it was the CC...statements made in the CC are made under threat of penalties, PRs are not.

But I'm sure you understand AMD's business MUCH better than anyone in the company...

LOL, I'd argue I know more about the realities of CPU design than the CFO. That's probably why they have him do the report and make it as non-committal as possible. But of course, you would interpret it with the most optimistic slant possible and use the same vague quote as "proof" of your own intepretation.

Well, have it your way, but from an engineering standpoint, what you said is ludicrous.

 

[Idontcare]

Originally posted by: Viditor
...keep in mind that these weren't MY words, they're from the CC:

Robert J Rivet

..."Our world-class manufacturing facility in Dresden continues to set benchmarks for operating performance, including yields and cycle types. We continue to execute our 45-nanometer strategy according to plan and we will start production at mature yields this summer"

Thank you Viditor for making your value-add contributions to this thread. (after-all the thread's title is "When will AMD's Shanghai CPU come to market?")

I personally don't take the time to listen to CC's even though I know I should because there's always good nuggets of info if you know how to read between the lines.

But it is really nice of you to take the time to post the relevant CC transcript info here for the education and betterment of the AT forums. You don't have to do it, but if you had not then I would not have realized some things about AMD's situation this year.

To me the CC info is very telling. Thanks for sharing it along with your personal interpretation of it. I may or may not agree with your interpretation of the CC but I hope I'm acceptably civil in handling any disagreements between our views in our discussions (we all deserve a little civility).

 

[Viditor]

Originally posted by: dmens

Originally posted by: Viditor
It wasn't a PR, it was the CC...statements made in the CC are made under threat of penalties, PRs are not.

But I'm sure you understand AMD's business MUCH better than anyone in the company...

LOL, I'd argue I know more about the realities of CPU design than the CFO. That's probably why they have him do the report and make it as non-committal as possible. But of course, you would interpret it with the most optimistic slant possible and use the same vague quote as "proof" of your own intepretation.

Well, have it your way, but from an engineering standpoint, what you said is ludicrous.

That would be fine, and as I don't really know (but do suspect) your experience with Intel on uA design, I'm usre that you can acquit yourself well in this field...but what does that have to do with yields on manufacturing at AMD?
I must assume that you have absolutely no experience with APM, and that you obviously have very little knowledge of AMD manufacturing and yields.

Here is a primer from 2005 on APM

APM is huge advantage for AMD in the area of yields...how much so, neither company will ever let us know.

 

[Phynaz]

You link says nothing about what APM is.
It's more of your AMD press release speak.

Nice lines "It is now believed at AMD that we should be able to bring new technologies into manufacturing at mature yields."

So he is saying before APM, AMD used to bring trechnologies into manufacturing before they were mature. Why do they ony "believe" that this "should" enable this? Don't they know? No wonder AMD is in the conidtion that are in.

Here's a clue for you, APM is statistical process control.
Every manufacturing company of any significant size uses it.

 

[lightstar]

speaking of AMD & barcelona, check out this article:

http://www.dailytech.com/Dodec...+Race/article11531.htm

 

[Idontcare]

Originally posted by: Viditor
APM is huge advantage for AMD in the area of yields...how much so, neither company will ever let us know.

I've seen the yield numbers for AMD, TI, TSMC, UMC, Chartered, Micron, Freescale and IBM.

I haven't met a person "in the know" in the industry who didn't consider AMD's APM the envy of any fab management platform.

I have also met plenty of people who liked to think they were in the know. For some reason merely drawing a paycheck from a given employer seems to convince some people they are imbued with knowledge of the inner-workings of their employer's business units.

I've literally observed janitors and dock workers do their best to "talk up" their understanding of the business workings of how fabs operate at TI. It becomes a parody to watch after a while. And it happens here on the forums all...the...time.

At any rate, I'm not really interested in whether anyone believes me or not, but for whatever its worth I have seen the numbers and walked the walk for more than a decade and AMD's APM is a massively beneficial asset. The only people I've ever heard try and undersell it or bash it are those individuals who have never actually had much to do with the business end of a fab.

Even the Intel assignees to Sematech expressed appreciation (and envy) for benefits of AMD's APM. But the APM system that AMD developed is not something that can be transplanted into a competitor's fab. It's not just a simple program to steal or reverse-engineer, nor is it something you can re-create by simply hiring enough of the right people from AMD and putting them into your fab.

It really is an entire system that involves the culture of how people think and operate in the fab environment when making improvements to equipment and process as well as tackling excursions and yield limiters. It works for AMD because their culture has been doing it for so long. It would be hard for anyone to attempt to copy-cat exactly what AMD has done.

Sigh...enough of me ranting on this, I think folks will either get the point or continue to want to believe what they believe.

 

[bryanW1995]

that's interesting...maybe they can get high enough yields that they'll be able to sell phenom x4's for $99 and compete with Q6600 finally on value.

 

[Kuzi]

Originally posted by: bryanW1995
that's interesting...maybe they can get high enough yields that they'll be able to sell phenom x4's for $99 and compete with Q6600 finally on value.

Phenom at 65nm is too big in size, I'm not sure if AMD is making much money selling them at the current prices, it's also a native quad core, which means yields will always be lower than a dual core for example, or two dual cores glued together

 

[Idontcare]

Originally posted by: bryanW1995
that's interesting...maybe they can get high enough yields that they'll be able to sell phenom x4's for $99 and compete with Q6600 finally on value.

The die-size of these monolithic quads are a real yield limiter. You can't escape the physical reality of larger dies means higher chances of surface defects killing a chip during fabrication.

You can't exect to make money in this industry if you have to create large chips merely to performance compete on the budget end. You need sizable margins on the chips you do sell to enable you to pay for all the silicon that reached the end of fab and turned out to be scrap.

Intel's MCM is the perfect strategy for competing in the budget end of the markets because it decouples the yields of their quadcore processors from the yields they would be realizing were their quads monolithic.

I have no doubt Intel is none too excited about moving their desktop and (gasp) budget segment quadcores to Nehalem. The yields are likely 20% lower (if not even more depressed than that) for a Nehalem quad over a Penryn quad of equivalent clockspeed...so unless Intel sees a way to make more profit selling the more expensive-to-manufacture Nehalems then I doubt we'll see much of an effort put into getting Nehalems into your sub $1000 desktop builds.

 

[bryanW1995]

yeah, I've been planning for almost a year now to just get a Q9450 now and then wait to get a nehalem in early 09, but it's looking more and more like that will be a VERY expensive move. Also, the core architecture is so strong that there's not much chance that paying $500+ for a nehalem cpu plus getting a new mobo and moving to ddr3 will yield enough benefit to make it worthwhile. I might end up just sitting this one out and waiting for westmere.

 

[Idontcare]

Originally posted by: bryanW1995
yeah, I've been planning for almost a year now to just get a Q9450 now and then wait to get a nehalem in early 09, but it's looking more and more like that will be a VERY expensive move. Also, the core architecture is so strong that there's not much chance that paying $500+ for a nehalem cpu plus getting a new mobo and moving to ddr3 will yield enough benefit to make it worthwhile. I might end up just sitting this one out and waiting for westmere.

I suspect a signficant percentage of us enthusiasts will be executing to this strategy as well.

It will take a shrink for Intel to get the Nehalem die size down to comparable levels of a wolfdale so that the yields (and thus manufacturing costs) are comparable so they can justify pricing them for a $200 ASP market.

Likewise it will take a shrink in order for the power consumption to come down such that it can be entertained as a viable platform migration option from the established LGA775 and LGA771 systems that have Yorkfield/Harpertown upgrade paths before reaching EOL.

Edit: dam just realized this is a Shanghai thread that I've now totally hijacked into an Intel thread. Sorry folks, my bad. Someone throw a wet-fish at me...

 

[Viditor]

Originally posted by: Idontcare

Originally posted by: bryanW1995
yeah, I've been planning for almost a year now to just get a Q9450 now and then wait to get a nehalem in early 09, but it's looking more and more like that will be a VERY expensive move. Also, the core architecture is so strong that there's not much chance that paying $500+ for a nehalem cpu plus getting a new mobo and moving to ddr3 will yield enough benefit to make it worthwhile. I might end up just sitting this one out and waiting for westmere.

I suspect a signficant percentage of us enthusiasts will be executing to this strategy as well.

It will take a shrink for Intel to get the Nehalem die size down to comparable levels of a wolfdale so that the yields (and thus manufacturing costs) are comparable so they can justify pricing them for a $200 ASP market.

Likewise it will take a shrink in order for the power consumption to come down such that it can be entertained as a viable platform migration option from the established LGA775 and LGA771 systems that have Yorkfield/Harpertown upgrade paths before reaching EOL.

Edit: dam just realized this is a Shanghai thread that I've now totally hijacked into an Intel thread. Sorry folks, my bad. Someone throw a wet-fish at me...

I think you guys have a very important discussion in the making there, and it effects both companies.
Maybe you should start a new thread (IMHO, it shouldn't be dropped).
As for throwing a wet fish:

1. you were just responding (though I think Bryan's point was a good one)
2. I'm gonna save it for Sea World...somehow I think it will be more fun there.