When did intel implement the tic-toc?

[Smoblikat]

I was just thinking that intel hasnt followed the tic-toc strategy in a while before IVB. They went from the Q9550, to the I7, to the 32nm I7 as their flagship processors (mainstream). Each time was a completely new arch and a massive speed boost. Am I missing somthng or did intel just forget about its own strategy?

 

[sefsefsefsef]

Conroe(65nm) --> Penryn(45nm)
Nehalem(45nm) --> Westmere(32nm)
Sandy Bridge(32nm) --> Ivy Bridge(22nm)

 

[Smoblikat]

Conroe(65nm) --> Penryn(45nm)
Nehalem(45nm) --> Westmere(32nm)
Sandy Bridge(32nm) --> Ivy Bridge(22nm)

I dont consider nehalem to westmere a tic or toc, they are same gen same series. Westmere is just the extreme edition.

 

[sefsefsefsef]

Then I guess you just don't know what Intel means when they say "tick-tock." "Tick" means a die shrink of the same architecture (like Westmere as a 32nm die shrink of Nehalem), and "tock" means a new architecture on the same manufacturing node (like Sandy Bridge as a new architecture on 32nm).

EDIT: there's actually a good wikipedia page on this topic -
http://en.wikipedia.org/wiki/Intel_Tick-Tock

 

[ShintaiDK]

Or bended in neon so to say.

 

[Plimogz]

^lol, pretty hard to argue with that.

 

[pantsaregood]

This isn't even a new strategy.

Katmai (250nm) -> Coppermine (180nm)
Willamette (180nm) -> Northwood (130nm)
Prescott (90nm) -> Cedar Mill (65nm)
Conroe (65nm) -> Penryn (45nm)
Nehalem (45nm) -> Westmere (32nm)
Sandy Bridge (32nm) -> Ivy Bridge (22nm)
Haswell (22nm) -> Broadwell (22nm)

"Tick Tock" has only been officially named since the Core 2 days. The fact is, however, Intel has been using die shrinks to test new process nodes for an extremely long time now.

 

[sefsefsefsef]

The new part is doing either a tick or a tock every ~12 months. Pentium 3 architecture was around for more than 2 years, and Pentium 4 architecture was around for 6 years.

 

[Arkaign]

They did die shrink/enhancements on 486s and 386s even.

 

[Homeles]

The new part is doing either a tick or a tock every ~12 months. Pentium 3 architecture was around for more than 2 years, and Pentium 4 architecture was around for 6 years.

This. Although P4 was tweaked a lot during those 6 years.

 

[Edrick]

I dont consider nehalem to westmere a tic or toc, they are same gen same series. Westmere is just the extreme edition.

Perhaps you should do a little more research.

 

[exar333]

This. Although P4 was tweaked a lot during those 6 years.

If by 'a lot' you mean 4 iterations in 8 years, then yes. Williamette inn 2000, Northwood in 2002, Prescott in 2004, and Cedar Mill in 2006. In that time, IPC was pretty flat, and speeds only went from around 2ghz to 3.8ghz (most being 3.4 or below).

I call these the 'lost years' for Intel.

 

[exar333]

Perhaps you should do a little more research.

This.

The whole idea of the tick-tock is to do alternating process shrink and new arch separately. Sometimes we get some 'special sauce' with the ticks like more cache, arch bonuses, or other things that provide a small IPC bump.

Tick - new process/more efficient/small IPC gain
Tock - new arch/small efficiency gain/medium-large IPC gain

 

[TuxDave]

I dont consider nehalem to westmere a tic or toc, they are same gen same series. Westmere is just the extreme edition.

You know what Intel's tick-tock cadence means right?

 

[pantsaregood]

If by 'a lot' you mean 4 iterations in 8 years, then yes. Williamette inn 2000, Northwood in 2002, Prescott in 2004, and Cedar Mill in 2006. In that time, IPC was pretty flat, and speeds only went from around 2ghz to 3.8ghz (most being 3.4 or below).

I call these the 'lost years' for Intel.

Pentium 4 went from 1.3 GHz to 3.8 GHz. Bus speeds went from 400 MT/s to 1066 MT/s.

Northwood was a die shrink of Willamette with doubled cache. It was pretty much identical otherwise. Prescott is, by comparison, quite distant from Willamette and Northwood. Prescott added support for (some models didn't enable all of these) SSE3, XD-bit, VT-x, EIST, and EM64T. It lengthened the pipeline significantly (which ultimately improved HyperThreading performance - it just wasn't noticeable back in 2004) and increased cache size. Cedar Mill eventually corrected the power consumption issues related to Intel's 90nm process, as well. Cedar Mill, of course, being a direct die shrink of Prescott.

The relationship between Willamette/Northwood and Prescott/Cedar Mill isn't too unlike the relationship between Pentium II and Pentium III. I'm surprised Intel didn't call Prescott "Pentium 5," honestly.

Intel's year-long cadence is what tick-tock brought. They've always used die shrinks of existing cores to test new process nodes. AMD has never had any predictable shrinkage/architecture process going on.

 

[Idontcare]

Every now in then, only once in a great while, I read one of these threads in the CPU forum where I literally can't tell if the OP is serious or just trolling...if OP is serious, then wow, just wow. If OP is just trolling the community, touche!

 

[IntelEnthusiast]

Every now in then, only once in a great while, I read one of these threads in the CPU forum where I literally can't tell if the OP is serious or just trolling...if OP is serious, then wow, just wow. If OP is just trolling the community, touche!

Thanks IDK I am just about to go into a meet but now I can laugh under my breath the whole time.

Tick-Tock is a business plan to help us ensure that we don't get stagnant with our designs and our technology. Every other year we do a die strink and on the off year we release a new microarchitecture.

 

[Red Hawk]

I was just thinking that intel hasnt followed the tic-toc strategy in a while before IVB. They went from the Q9550, to the I7, to the 32nm I7 as their flagship processors (mainstream). Each time was a completely new arch and a massive speed boost. Am I missing somthng or did intel just forget about its own strategy?

Maybe you don't actually understand Intel's strategy (or simply are trolling, as Idontcare suggested). Intel has stayed pretty close to its tick-tock strategy since the release of Conroe, 65 nm Core 2 Duo. Tick-tock isn't about "flagship", it's about architecture and process technology. Conroe was a tock, Penryn was a tick; Nehalem was a tock, Westmere was a tick (as it IS a die shrink of Nehalem from 45 nm to 32 nm); Sandy Bridge was a tock, Ivy Bridge was a tick.

I'm not sure what you were thinking of...maybe the Ke$ha song?

 

[nyker96]

amd needs to implement tic-tac-toe, the next level of tic-tac to beat intel ;]