what's with the original memory limitation on x86?

[jhu]

why did intel limit the original 8086 to 1mb of memory? it seemed to me that if they changed the way segmentffset was implemented, the chip could have 4gb of memory directly addressable (2^20 vs. 2^32).

 

[Smilin]

Originally posted by: jhu
why did intel limit the original 8086 to 1mb of memory? it seemed to me that if they changed the way segmentffset was implemented, the chip could have 4gb of memory directly addressable (2^20 vs. 2^32).

Never made sense to me either. Plus the fact you could have two different segment : offset combinations that point to the same location in memory. If you've ever used PC assembly language plus any other architecture's assembly language it gives you a new appreciation of just how sh1tty pc's are because of that 640k barrier.

Just count your blessings we aren't looking at segment : offsets again in the 32 bit world as we try to get past the 4gig barrier.

 

[Peter]

Well, the chip had only 20 address lines, physically, and 2^20 bytes = 1 MByte. Whether segment/offset addressing is stupid or not is an entirely different topic.

The big mistake made was designing the AT to be hardware compatible to the original PC, keeping the below-1-MByte memory map the same instead of moving all the I/O up to the end of the 80286's 24-bit memory space. Need I say GateA20?

 

[jhu]

why were there only 20 address lines? also, why's amd using only allowing 2^40mb of memory on their opteron?

 

[Peter]

The answer is, because the chips were designed that way. Chips are designed with reasonable headroom for the market they're going into, but not with ridiculous headroom - that would drive cost up.
So there, back when the 8088 first ended up in the IBM PC, 1 MByte of address space was reasonably well sized. 16 MBytes as found in the AT was plenty for quite a while, the 386 extended that to 4 GBytes, the Pentium Pro then to 64 GBytes. Opteron now going for 40 bits (which is one Terabyte!) is going to be waaaay plenty for the market they're aiming at.

 

[Mday]

Originally posted by: Peter
The answer is, because the chips were designed that way. Chips are designed with reasonable headroom for the market they're going into, but not with ridiculous headroom - that would drive cost up.
So there, back when the 8088 first ended up in the IBM PC, 1 MByte of address space was reasonably well sized. 16 MBytes as found in the AT was plenty for quite a while, the 386 extended that to 4 GBytes, the Pentium Pro then to 64 GBytes. Opteron now going for 40 bits (which is one Terabyte!) is going to be waaaay plenty for the market they're aiming at.

not to mention memory was VERY EXPENSIVE.

this was the mistake they made on one of the pentium chipsets which was limited to 64MB of RAM. i forgot what the chipset was. maybe it was the 430.

 

[CTho9305]

Originally posted by: Mday

Originally posted by: Peter
The answer is, because the chips were designed that way. Chips are designed with reasonable headroom for the market they're going into, but not with ridiculous headroom - that would drive cost up.
So there, back when the 8088 first ended up in the IBM PC, 1 MByte of address space was reasonably well sized. 16 MBytes as found in the AT was plenty for quite a while, the 386 extended that to 4 GBytes, the Pentium Pro then to 64 GBytes. Opteron now going for 40 bits (which is one Terabyte!) is going to be waaaay plenty for the market they're aiming at.

not to mention memory was VERY EXPENSIVE.

this was the mistake they made on one of the pentium chipsets which was limited to 64MB of RAM. i forgot what the chipset was. maybe it was the 430.

I thought you could use more, but it wasn't cacheable, resulting in a HUGE performance hit?

 

[Peter]

I thought you could use more, but it wasn't cacheable, resulting in a HUGE performance hit?

Most socket-7 chipsets did have a cacheability limit, anywhere from 64 to 512 MBytes of RAM depending on chipset and amount of L2 cache. However that only affected the lowest level of cache (on the mainboard), not the caches in the CPU. There is a performance hit to that, but it was WAY overhyped. Besides, not having enough memory for the application is orders of magnitude worse than L2- or L3-uncached memory.

 

[Nothinman]

also, why's amd using only allowing 2^40mb of memory on their opteron?

Because as someone said that gives you ~1TB of VM to play with, which is a lot more than most places need right now. The real benefit isn't in the max total memory, hell you can put 64G in an Intel box right now with PAE but each process is still limited to 4G (with 2G of that being reserved for the kernel in Windows and 1G in Linux) so you hit a ceiling at 2G which isn't that much any more.

 

[Smilin]

Originally posted by: Peter
Well, the chip had only 20 address lines, physically, and 2^20 bytes = 1 MByte. Whether segment/offset addressing is stupid or not is an entirely different topic.

Aha the answer I was looking for! "Physically" being the key word here. Thank you much sir!

 

[jhu]

Because as someone said that gives you ~1TB of VM to play with, which is a lot more than most places need right now.

that's what we said of 4gb 10 years ago. just bring it up to the max. how much more silicon does it cost?

 

[Nothinman]

That's what we said of 4gb 10 years ago. just bring it up to the max. how much more silicon does it cost?

Get an alpha, they use 42-bits for ~4TB of VM.

 

[Smilin]

Originally posted by: jhu
Because as someone said that gives you ~1TB of VM to play with, which is a lot more than most places need right now.

that's what we said of 4gb 10 years ago. just bring it up to the max. how much more silicon does it cost?

I'm betting that adding addressing would cost a LOT more silicon. You'de have to expand nearly every portion of the chip.

 

[Basse]

Originally posted by: jhu
Because as someone said that gives you ~1TB of VM to play with, which is a lot more than most places need right now.

that's what we said of 4gb 10 years ago. just bring it up to the max. how much more silicon does it cost?

And if you would wait another ten years from now it may well be @ 1000TB ~ 1PB. I mean, who really uses 1TB today, or even 4GB? No point in implementing it if it costs more and isn't needed by users today.

 

[Nothinman]

I mean, who really uses 1TB today, or even 4GB? No point in implementing it if it costs more and isn't needed by users today.

A lot of databases, 3D rendering, huge image processing, etc apps need more than 4G (well 2G on Windows and 3G on Linux because of the kernel reserved space). No, most people don't need the address space increase, but Microsoft sure does because MS SQL can't really compete against Oracle when Oracle can run on a Sun box with 1TB of memory and use as much of it as it needs and MS SQL is stuck running on Windows and has a ceiling of 2G.

 

[Basse]

Originally posted by: Nothinman

I mean, who really uses 1TB today, or even 4GB? No point in implementing it if it costs more and isn't needed by users today.

A lot of databases, 3D rendering, huge image processing, etc apps need more than 4G (well 2G on Windows and 3G on Linux because of the kernel reserved space). No, most people don't need the address space increase, but Microsoft sure does because MS SQL can't really compete against Oracle when Oracle can run on a Sun box with 1TB of memory and use as much of it as it needs and MS SQL is stuck running on Windows and has a ceiling of 2G.

I know this, and it still doesn't justify the additional cost of implementing it. I know you understand, just wanted to clarify my pow.

 

[Nothinman]

I know this, and it still doesn't justify the additional cost of implementing it. I know you understand, just wanted to clarify my pow.

OK, sorry. I wonder how much it would actually cost. Alphas have used 42-bits for quite some time now, you'd think AMD would atleast match them. Anybody know off hand how many IA64 is currently using?

 

[TerryMathews]

Originally posted by: jhu
also, why's amd using only allowing 2^40mb of memory on their opteron?

I'm no expert, but I was under the assumption that each Opteron had it's own memory controller, so each Opteron can address 1TB of memory? So a quad box could theoretically address 4TB of memory?

 

[Nothinman]

I'm no expert, but I was under the assumption that each Opteron had it's own memory controller, so each Opteron can address 1TB of memory? So a quad box could theoretically address 4TB of memory?

The problem limitation isn't total memory in the box, you can put 64G in an Intel box using PAE hacks. The problem is per-process limitations, on a 32-bit box that's ~4G (with part of that being split off for kernel use) and on an Alpha that's ~4TB and on an Opteron that ~1TB. So even if you have 4TB of memory in the box, any 1 process will only be able to address 1TB of it (I don't know what the user/kernel split ratio is though).

 

[Demon-Xanth]

430 chipset trivia:
430FX, 430VX: 64MB cachable, 128MB max
430TX: 64MB cachable, 256MB max
430NX, 430HX w/o 512kB L2 w/ TAGRAM: 64MB cachable, 128MB max
w/: 512MB max and cachable.

Wanna guess which chipsets were considered high end?

 

[Peter]

Not quite.

430HX with 256 or 512 KByte L2 cache, and 8-bit TAGRAM had 64 MByte L2-cacheable area. With 11-bit-wide TAGRAM, it's 512 MBytes. Remember the CPU cache(s) always covers all the RAM, even if the mainboard's cache doesn't.

 

[kpb]

The cost for upping the memory address bus from 40 to 48bits is space on the chip. To add those 8 bits you need to add 8 more paths any place a memory address is transfered. The opteron is already planned to be a pretty large chip from what I've read so adding 20% more paths everywhere that you have memory addressing could add a fair bit to the chip size and make it noticably more expensive to produce.

Also if i'm not mistaken they could fairly easily increase it from 40 to 48 bits or even 64 bits in a future chip with out having to do a compleate redesign or further changes to the ISA like they are having to do to go from 32 to 40 since the architecture is 64bit.

 

[Nothinman]

Also if i'm not mistaken they could fairly easily increase it from 40 to 48 bits or even 64 bits in a future chip with out having to do a compleate redesign or further changes to the ISA like they are having to do to go from 32 to 40 since the architecture is 64bit.

That's probably true, but it would still require software updates because you know people would make assumptions about the size of certain data types.

 

[CTho9305]

Originally posted by: Nothinman

Also if i'm not mistaken they could fairly easily increase it from 40 to 48 bits or even 64 bits in a future chip with out having to do a compleate redesign or further changes to the ISA like they are having to do to go from 32 to 40 since the architecture is 64bit.

That's probably true, but it would still require software updates because you know people would make assumptions about the size of certain data types.

I woudl think it is easier to assume 64 than 48...

 

[glugglug]

The 1st Opterons only have 40 external address pins on the outside of the chip, for accessing 1TB of physical memory. I think the MMU can handle a 48-bit (256TB) virtual address space, not sure on that though.

Since the registers are already 64-bit including address registers there is nothing keeping them from expanding to 64-bit addressing on a later version completely transparent to software except on the OS/Virtual Memory Manager level.