Ah, I see we're getting somewhere.
>Well, since I do all my work in Windows, not DOS, I am more concerned with how the memory performs in Windows.
You still got a multitasking OS interfering. If you really want to measure latencies and throughput and see accurate numbers, use DOS and CACHEMEM.
>Intel designed the PCI bus, didn't they?
Not really. They initiated its development, but multiple companies (the "Steering Group") were and still are actively developping the standard(s).
www.pcisig.com is the place where it all happens.
>Regardless, I was basing my statements about PCI bus parking off of information that I had read before that seemed pretty credible. However, it is possible that this information was wrong.
Yes, there's been plenty inaccurate or even plain wrong guesswork in the press - most of it following VIA's announcement that they're going to implement bus parking to make those buggy cards work anyway. It's a niceness move from VIA to make users happy although the actual fault lies elsewhere, yet still it's been misinterpreted as VIA confessing that they've been lacking something important. Bashing VIA is just too darn tempting, it seems. (Same story as with the original SB!Live bug that still is widely attributed to the VIA 686B south bridge ...)
>Hmmm... interesting. I didn't know the problem existed with SiS chipsets too. The only time my friend had sound crackling problems with his ECS K7S5A was because he was using a PCI graphics card.
The latter problem is PCI bus bandwidth hitting the ceiling, not related to said SB!Live bug. What happens if you plug an SB!Live (original series, the 5.1 series had that fixed) into an SiS chipset mainboard, most of them will plain hang upon booting Windows. YMMV - it's a timing issue, actual results differ from mainboard to mainboard.
>This is not true. The ALi southbridge supports ATA-133. Maybe I'm just bad at math, but how does this exceed the PCI bus bandwidth of 133 MB/s?
Well you got two independent IDE channels there, that's 266 MB/s in my flavor of math ... besides, there's other stuff in the south bridge (USB, sound, power management, ISA bridge to frequently accessed legacy I/O like the system interrupt controller, system timers, keyboard, mouse, floppy, COM and LPT ports) that also needs some bandwidth. All taken together, there's much less left for PCI cards than on chipsets that don't have the south bridge on PCI.
VIA V-Link btw has been stepped up to 533 MB/s for the 8235 south bridge, SiS MuTIOL is at 1 GB/s already (963 south bridge). Basically everyone has made the move away from using 32-bit 33 MHz PCI as the system backbone, except ALi and ATi (mainly because they use ALi and older VIA south bridges). Intel uses their own HubLink, AMD uses twin PCI busses (66 MHz north-south, and 33 MHz behind the south) and will use HyperTransport on K8, NVidia uses HT already.
regards, Peter