What the likelihood that the revised Athlon64 might have an L1 cache of 256k?

[MadRat]

It follows with AMDs design progression:

K5 16k L1
K6 32k L1
K6-2 64k L1
K7 128k L1
Pre-release K8 128k L1
Delayed K8 ?256k L1

The reports that ClawHammer has ONLY a paultry 256k of cache would tend to be believeable if it had an L1 cache of 256k.

It would also explain the latest delay for the release.

 

[Wingznut]

The likelyhood... slim and none. It would practically require a complete redesign, a completely new set of masks, and would be much more than a six month delay.

 

[First]

No, the question is how AMD will deal with the A64's L2 cache. 1024KB at release probably isn't out of the question, though perhaps they'll just start out with 256KB or 512KB parts before moving to 1024KB. Or maybe they'll release Opertons with 1024KB L2 in addition to dual channel functionality. Who knows!

128KB L1 is probably going to stay the same btw.

 

[paralazarguer]

What the likelihood that the revised Athlon64 might have an L1 cache of 256k?

Absolutely zero. They will have the same L1 cache that the athlon XP has now (128K total) and have only 256K L2. The opteron will have more cache though.

 

[paralazarguer]

And wait...what do you mean revised Athlon 64? Do you mean like the third or fourth version or do you mean the release version which has been delayed?

 

[magomago]

That would be interesting to see them come out with 256 or 384 L1 Cache with 1024 meg L2 Caches perhaps a year after the A64

Talk about a preformance increase

 

[Wingznut]

Originally posted by: paralazarguer

What the likelihood that the revised Athlon64 might have an L1 cache of 256k?

Absolutely zero. They will have the same L1 cache that the athlon XP has now (128K total) and have only 256K L2. The opteron will have more cache though.

From what I understand, the plan was that Clawhammer will be offered in both 256k and 1mb L2 flavors.

 

[magomago]

Wingnutz, if you don't mind me asking, what is a lithography technician? Does that mean you actually produce the .13 u P4s? Just wondering...

 

[MadRat]

So, Wingz, you would be implying that if they do make a shift to a 256k L1 then it would more likely happen during a switch, say from 130nm to 90nm?

I would hope that AMD already has worked out the kinks for a 256k L1 cache being that the 128k L1 has been around now for several years and its outlived its time. AMD banks their main cache design around the L1 cache whereas Intel banks their design around the L2 cache. AMD saved development time of the Thoroughbred by sticking to the 128k L1 cache rather than jumping to a new L1 design. But that meant that the 128k L1 has survived three different processes, 250nm, 180nm, and 130nm.

Heck, if they had done a 256k L1 cache then Thoroughbred would have been fine to release w/o an L2 cache, making it like a Duron to compete with the P4, and Barton could have been a simpler 256k L2 cache design!

 

[Baronz]

Originally posted by: paralazarguer

What the likelihood that the revised Athlon64 might have an L1 cache of 256k?

Absolutely zero. They will have the same L1 cache that the athlon XP has now (128K total) and have only 256K L2. The opteron will have more cache though.

The Clawhammer will have 1mb L2.

 

[JeremiahTheGreat]

From what i understand,

the 256kb L2 cache version of Athlon 64 is prolly for mainstream users..

while the 1Mb L2 cache version of Athlon 64 is for dual processor, and high performance.

 

[Wingznut]

Originally posted by: JeremiahTheGreat
From what i understand,

the 256kb L2 cache version of Athlon 64 is prolly for mainstream users..

while the 1Mb L2 cache version of Athlon 64 is for dual processor, and high performance.

Yeah, that's what I've heard too. It is expected that the overwhelming majority of Clawhammers sold will be of the 256k flavor.

 

[Nemesis77]

What I would like to see is Clawhammer with 512K of L1-cache and 4megs of L2-cache . But it's not gonna happen. Not for several years at least . But hey, one can always dream !

 

[bgeh]

there'll be 2 flavours of the Athlon 64
the Athlon 64(Paris) will feature 256kb L2 cache
the Athlon 64(Clawhammer) will feature 1MB L2 cache

 

[Accord99]

Originally posted by: MadRat
It follows with AMDs design progression:

K5 16k L1
K6 32k L1
K6-2 64k L1
K7 128k L1
Pre-release K8 128k L1
Delayed K8 ?256k L1

The entire K6 series had 64K L1 cache. But it had a 2 cycle latency, while the Athlon has 3 cycles.

It would also explain the latest delay for the release.

I doubt it. Doubling the L1 cache may not necessarily lead to any performance gains since it will at best, improve the cache hit rate by a couple of % (the Athlon's L1 cache already has a ~95% hit rate on average realworld code), while likely resulting in reduced core scalability and/or increased cache latency. At the present, a trilevel cache hiearacy seems to be the preferred method to go for all of the modern high end 64 bit processors; Itanium, Power and Alpha series, so that might well be the future of desktop cpus.

 

[RSMemphis]

I doubt a large L1 cache will help that much. Look at the PIV, it has a paltry L1 cache, and it does not do badly (although not as good as the Athlon XP clock for clock).
Hitting the full-speed L2 does not cost the processor much, maybe one/two clock cycles. That's not a lot, and not enough to justify bumping the L1.

Honestly, it really just all depends on how well the Athlon64 will scale. Again, I doubt that games will profit much (if anything) from the 32/64 architecture.
I think it will excel as a number cruncher, mostly. As does, for instance, the Barton.

 

[MadRat]

You cannot compare the L1 cache of the P4 to the Athlon's L1.

If you look at the P4 specs, its L2 cache has a similar functon to the L1 cache of the Athlon. The P4's L1 cache is actually very slow compared to its L2 cache because it doesn't need to be full-speed. I believe the P4 also does its searches through its L2 then pulls from the L1, if the data is available there, because it doesn't stall an instruction if the data is in the L1.

 

[yhelothar]

isn't the point of the L1 cache is that it's small so it has low latency? Putting more on would only make it slower... i think 128KB is about the highest it would do any good..

 

[MadRat]

That may have been true at 500MHz, but they already broke 2GHz now. The length of the instruction pipeline is slightly longer nowadays so adding one more cycle of latency isn't going to kill it. The 2-cycle latency of the P4 L1 cache matches the timing that is necessary to sustain a transaction on the fly. AMD may eventually use this type of L1 cache and then its current L1 cache would be bumped to the L2 name...

 

[imgod2u]

I don't see why hyperpipelining would make cache latency less important. If anything, it's more important. At extremely high clockrates, having low-latency cache access is crucial to avoid pipeline stalls. The P4's L1 data cache, btw, has a very low latency compared to the L2 (which has a 7 cycle transfer latency for a 64 byte cacheline I think). Increasing cache size, as others have pointed out, would only increase cache latency and would probably serve very little purpose. Extra storage can always be attained by increasing the L2 cache size or adding an L3 cache. The L1 is there to provide ultra-low latency access to data in the case of cache hits.

 

[paralazarguer]

the 256kb L2 cache version of Athlon 64 is prolly for mainstream users..

while the 1Mb L2 cache version of Athlon 64 is for dual processor, and high performance.

Yes, this is true. It's like the difference between the athlon XP and that athlon MP. Then there's the opteron on top of this. Generally, people are going to be buying the 256K version for home use...

 

[MadRat]

Originally posted by: imgod2u
I don't see why hyperpipelining would make cache latency less important. If anything, it's more important. At extremely high clockrates, having low-latency cache access is crucial to avoid pipeline stalls. The P4's L1 data cache, btw, has a very low latency compared to the L2 (which has a 7 cycle transfer latency for a 64 byte cacheline I think). Increasing cache size, as others have pointed out, would only increase cache latency and would probably serve very little purpose. Extra storage can always be attained by increasing the L2 cache size or adding an L3 cache. The L1 is there to provide ultra-low latency access to data in the case of cache hits.

But AMD's philosophy on the L1 cache is not similar to Intel's in the way they approach the design. AMD uses the L1 cache similar to what Intel uses their P4's L2 cache. The P4 doesn't have an equivalent cache to the Athlon's L2 cache else it would be an L3 cache. I think AMD would be able to squeeze 256k into their L1 cache with little to no penalty in timing. AMD would make the need for the current L2 in consumer CPUs if they did this, especially if they introduced the microOps cache like Intel uses in their P4 L1 cache.

I'm guessing that AMD was looking for simplicity in the initial Hammer design but will make a big change with something in the design here soon. It makes alot of sense especially if this delay had more to do with the design than Microsoft and their 64-bit Windows OS. There is already a 64-bit Linux out there to tease programmers with the design of the Hammer family.

 

[imgod2u]

If they provided another, higher level of low-latency cache, wouldn't they just call it L1? And have the current cache that's called L1 be the L2 cache. In which case, we're just talking about a redesign of the cache architecture in which they would adopt a similar caching structure to the one Intel uses. However, I do see your point that the K7 treats its L1 cache not really like an L1 cache at all, but rather like a slightly higher-speed L2. But then, what would be the benefit from increasing it to 256KB? Why not just have a slightly faster L2 cache?

 

[MadRat]

I'd imagine to reduce latency in a meaningful way then AMD either will need to reduce the size, which is contrary to their philosophy OR they'd introduce a microOps L1 cache like the P4 architecture. The problem is that with the microOps L1 cache a mere 128k L2 cache would be pretty flimsy for performance.

The way they currently use the L2 cache then it wouldn't improve performance by more than 10-cycles of latency by increasing its speed even by 100%. AMD has demonstrated the feasibility of a 512k L2 cache and its not near as an increase on performance as the rise in cost implied. Increasing the L2 cache size was cheaper and lower risk than increasing its speed, which is the most likely reason they chose this route. Its probably less risky to double the L2 cache than the L1 cache and IMO to increase the L2 cache speed would be even more risky than doubling the L1 cache. But with 256k of L1 then AMD would still have a viable chance to sell half-disabled or quarter-disabled L1 cache HAMMER chips if the yields with fully working L1's were too low.

Then again as delayed as the K5 through K7 were, perhaps increases in the L1 cache is not worth the trouble on the immediate launch.