Adding a third CCX on a 7nm shrunk version of the existing 14/12nm product would still result in a markedly smaller die. The way IF works allows them to effectively just add another item on the fabric without requiring a wholesale tear up of the logic (a 7nm shrink that is anything more than a dumb shrink will require a new floorplan no matter what). Another CCX will add 8 more MB of L3 cache and will lean on the IF more heavily for CCX <-> CCX communications for cache coherency, etc. To keep this from harming thread performance, there will need to be an increase in IF throughput, probably by clocking it higher. With a smaller die and an improved process, this shouldn't be too big of a problem when looking from afar. The next issue would be RAM bandwidth demands. Keeping 12 cores and 24 threads fed with data is not going to be easy. Qualifying for higher speed RAM can help, but there will still be issues there. I suspect that there will be an additional effort to mitigate the data bandwidth requirements at 7nm, perhaps by introducing an exclusive L4 cache in the 64MB range on die, enabled at various sizes depending on the product tier. The move to 7nm enables this while still fitting in the existing footprint of the 12nm die.
Going forward, I suspect that AMD may introduce a modification of the AM4 socket that will support triple channel RAM. As the cores get faster, and the core count increases, the demands on RAM bandwidth will continue to grow and something will need to give. This would have implications for TR and EPYC as well. I suspect that trying to support 12 DDR channels on the EPYC package would be a path routing nightmare, but perhaps a 6 channel TR may not be beyond the realm of possibility. Has anyone ever considered the possibility of using SO-DIMMS in a desktop, workstation or server platform to keep board real estate usage in check? I know I've seen them in the mini-itx format before.
I don't think that much will change with the APUs in the short term. They are value products in the desktop space and won't support an expensive change in platform. I suspect that they will get a 7nm core shrink like the rest of the stack. They might get split into two different product lines at first, with an early 7nm product being another 4 core chip with a similarly sized (though perhaps graphics IP refreshed) iGPU and later a 2 CCX, 8 core product with the same GPU setup that is destined for mid-range mobile products (this will require another die, but I believe volume and revenue will support that by that time). At some point, I suspect that AMD will introduce a mobile MCM product that has a 7nm die and either a dGPU chip with HBM ram on it (similar to Intel's KL-G) or, perhaps they will do an APU die based around their 7nm Zen cores, a larger iGPU section, but with an HBM controller embedded IN ADDITION TO the two channel DDR controller that can be enabled or disabled as needed. This would allow a product that could be mounted in a normal package with no HBM for a mid-range mobile solution or be mounted on an MCM with HBM on a higher end solution. This would allow AMD to leverage their greater ability to integrate a high performance gpu with a high performance processor as opposed to Intel that currently has to bundle a separate dGPU chip on their EMIB package. This would reduce the disadvantage that AMD has by using MCM, but allow them to keep a similar footprint.
This is all just educated guesses on my part.