What is the Celeron's microarchitecture at last?Let's discuss...

[dbal]

I copy from Anand's review of the first P4Celeron@1,7Ghz:
"The new Celeron core is based on a 128KB L2 version of the original Willamette core that the Pentium 4 debuted with in November of 2000. Unlike previous-generation Celerons, the Willamette-128 core is no different architecturally than the Pentium 4's old Willamette core. The cache organization and mapping algorithms are still the same, the only difference is that the Celeron core is only outfitted with a 128KB L2 cache instead of the 256KB cache present on the original Pentium 4........
......For information on the NetBurst architecture behind the Celeron take a look at our one page explanation of its strengths and weaknesses"
So everyone assumes that the existing Celeron line (Wilammette or Northwood core) is built upon the Intel NetBurst microarchitecture.....
In addition we all know that sharing the same Northwood core i.e. doesn't mean spontaneously, that the cpus follow the same microarchitecture, right?
The confusion starts from a closer look in Intel's site that clearly states for every Celeron cpu up to date that it follows the old P6 architecture with some minor improvements taken from the NetBurst like the 400Mhz bus.
Please check the following links:
About P4's Netburst
About the Celey's P6 structure
that are exactly correpondent to each other in the site's structure, referring to the same stuff for each processor.

So, are we in front of a deeper explanation for the Celey's poor performance to all respective Pentium4s aside the simple "less L2 cache" issue or am I somewhere seriously mistaken?
Eager to all explanations and the much desired right answer...!

 

[jjyiz28]

i don't know much about the architecture, but when the willamettes first came out, were it not underperforming even a thunderbird?? like doesn't a 1.4 thunderbird absolutely kill a 1.4 willamette?? only when the northwoods came out with double L2 cache did performance substantially increase. therefore if you could imagine crippling an already crippled chip (willamette) which is basically what a celeron is.

 

[Booster]

It's the same Willamette chip, IMO, b/c otherwise it would be a huge waste to design a completely different chip. What Intel does is (basically the same method they used with a Coppermine Celeron):

1 Spot P4 Willamete chips with bad blocks in the second 128KB half of cache
2 Disable that half
3 Turn off some advanced features, like the hardware prefetch was turned off for Tualatin Celerons (that's why they aren't of the same performance as the PIII, it would hurt PIII sales otherwise).

However, in the result you'd not only get a lesser performing chip, but also a chip with half the L2 cache bandwidth (b/c switching off the second half of the cache leads to decreased associativity - 4-way instead of 8-way for the full P4).

In the case with Northwood, the L2 cache bandwidth is decreased by 4 times... That, I think, is the reason for poorly performing Celerons, not only smaller L2 cache. Overall reduction is speed is at least 20-25% in all applications and up to 50-60% in specific CPU-intensive tasks which are cache-hungry.

 

[yodayoda]

celerons have always been dogs at performance. only when you heavily OC them do they show some sparks of life. a 1.3GHz duron makes mincement of this chip. i think you are better off getting a 1700+ for $50. at stock speed it trounces the celeron and when you OC up to 2 GHz, it eats it alive.

 

[dbal]

All input finds me absolutely consistent but the Celeron's poor performance is a known issue to me. I mainly want to focus on the reason which for me, is the lack of the P4's Netburst architecture in contrast to what we thought till now-even Anand's review of it.....Tell me if I am wrong....

P.S:

Originally posted by: yodayoda
only when you heavily OC them do they show some sparks of life.

Could you guess the performance difference between a 1,5Ghz P4 and a 2,2 Ghz Celeron (Nwood) o/ced to 2,9Gigs? Would it be on par at least in 3D Gaming??

 

[imgod2u]

There's a chart on that page you listed that lists the architectural features of the Celeron at different frequencies. The Celerons from 1.7-2.0 GHz listed both the Hyperpipelined design, execution trace cache, rapid execution engine and SSE2. The list from 2.0 to 2.2 GHz listed this as well but on the .13 micron copper process.

 

[dbal]

You are right imgod2u! This much answers the issue I raised since the only pieces missing now from the Celeron's Netburst pie are Advanced Dynamic Execution Engine and Data Prefetch Logic......(Any hints on this??)
Still noone understands though why Intel here refers to a P6 architecture design and not clearly Netburst for the 1.7Ghz+ Celeron line....Could they be deliberately hiding such info for the average user so they increase the market gap between the target groups of the 2 processors?I really tend to strongly believe this....

P.S: In any case, the site is a piece of crap...Trying to access the same info (e.g about the celeron) from different ways (Products, Home computing, Processor design) gets you to totally controversial content like the issue we are talking about-pity....:disgust:

 

[dbal]

bump

 

[Boitch]

If you take a look at the INTEL Page you pointed out, there is also on the left-hand coloumn documentation about the CELERON specifications, which u can download in PDF format.

The link is:

http://www.intel.com/design/celeron/datashts/251748.htm

If you read this datasheet (478 Nothwood core), you will quickly see that this CELERON does indeed include the REE (Rapid Execution Engine), and Advanced Dynamic Execution engine, which includes Enhanced Branch Prediction.
There are 99 Pages of reading material for u, so have fun.

This tells me that the limitating factor is indeed the cache, though INTEL did not specify (or admit) whether ALL of
these features are indeed fully ENABLED.

 

[Lyfer]

Its a northwood with less cache. Simple as that. And btw an XP1700 at stock speeds will dominate a celery 2.4GHZ.

 

[pspada]

The reason for the Celery's poor performance is obvious - Intel needs to have an alternative, lower cost processor to offer instead of having customers move to AMD chips. Of course anyone with a brain can figure out that an AMD is a better chip at a lower cost, but some folks are bothered if they don't get "Intel inside", and Intel's marketing wins again.

 

[hans007]

celerons are slow because of the cache for this reason.


the new celerons i think are up to 2.6ghz already , and based on northwood. the reason p4 architecture chips need large fast caches, is that they have a 17 or 20 stage pipeline (i dont remember but its deep).


when you process instructions, many instructions are dependant on the results of preceding instructions.

i.e

a=b+c
z=a+2;

you cant process the 2nd one without finishin a=b+c;

so.... if say the variable B is not in cache (and its less likely to be in a 128k l2 cache chip like a celeron) then it has to go to main memory which is very slow. and at 400mhz bus, that is even slower (celeron probably wouldnt be nearly as bad on 800mhz bus).


so... thats why the latency penalty of rdram was bad, it slowed the memory access.


if it has to wait for memory, all the later instructions are waiting for this one instruction. thus a pipeline stall. and with more pipeline stages, more instructions are stalled in queue. thus the slowdown.

 

[Lonyo]

What will Intel do when they move to Prescott? Might they use a current Northwood core as the basis of the Celeron, or will they use a variation of Prescott core, as the current architecture seems to be reaching some speed limits.
A neutered Prescott might work, or a smaller process for the current architecture, but does anyone know anything real about what Intel will do to continue their budget line, if anything?