what is so much better about hypertransport than a regular FSB?

[hosto]

What is better about hypertransport over a normal front side bus?

I mean, the hypertransport bus appears to run at 800mhz which is the same as the P4's 800mhz FSB

 

[miketheidiot]

lower latency because the memeory controller is integrated into the chip.

 

[hosto]

yeah but the onboard memory controller isnt hypertransport is it?

 

[masshass81]

^ I'm not too clear about this either, someone please clarify difference between FSB and Hypertransport!

 

[miketheidiot]

its also a direct connection between processors in multi-processor systems or to chipset/peripherials in a single processor setup. Im not sure if that parts completely accurate though.

 

[iwantanewcomputer]

i think it means the processor connects directly to other cpus and the memory(maybe agp and pci components) instead of routing through the northbridge. in a single processor system i think it's the same as a fsb, except maybe in connecting to the memory

 

[hosto]

it is a tricky one, can you throw us a frickin bone here jonny?

 

[justly]

For the end user I don?t think they will see much of a difference. Hyper transport benefits have more to do with ease of implementation, lower latency and data integrity from what I understand. There are other benefits also but for the most part the end user only benefits from lower latency and the reduced cost of implementation.

You might want to read some of the FAQ at http://www.hypertransport.org/faqs.html (NR 9 & 10 compare some bus technologies against HT but quite a few of the other FAQ also have some interesting tidbits).

 

[BW86]

http://www.ocforums.com/showthread.php?t=306418

Traditionally, a Northbridge exists between the memory bus and the CPU. The rate at which data is transferred between the memory and CPU is known as the front side bus. However, the Athlon64?s memory controller is on-die, and as such, has no Northbridge, nor a front side bus. The Athlon64?s have two independent buses; one between the memory and the on-die controller, and another bus that communicates with the other system devices- the HyperTransport bus.

 

[Mik3y]

hypertransport works 800mhz one way, and 800mhz the other way. that's why the hypertransport speed is 1600MHz. now you get the idea of what 2000mhz hypertransport is when it comes out soon.

 

[hosto]

farout...i can now see why the athlon64 has so much bandwidth and snappy performance in windows now

 

[klah]

HyperTransport I/O Technology Comparison With Traditional And Emerging I/O Technologies
http://www.hypertransport.org/...hitePaper_HTC_WP04.pdf

 

[BW86]

Originally posted by: Mik3y
hypertransport works 800mhz one way, and 800mhz the other way. that's why the hypertransport speed is 1600MHz. now you get the idea of what 2000mhz hypertransport is when it comes out soon.

i thought a 2000mhz HTT is out now? dont the nforce3-250 chipsets support up to 1000mhz HTT?

 

[masshass81]

Originally posted by: BW86
http://www.ocforums.com/showthread.php?t=306418

Traditionally, a Northbridge exists between the memory bus and the CPU. The rate at which data is transferred between the memory and CPU is known as the front side bus. However, the Athlon64?s memory controller is on-die, and as such, has no Northbridge, nor a front side bus. The Athlon64?s have two independent buses; one between the memory and the on-die controller, and another bus that communicates with the other system devices- the HyperTransport bus.

Thats what I was thinking, but then I see VIA chipsets have a Northbridge and a Southbridge... whats up with that??

Example...

 

[imported_incubus]

maashass81..

maybe it's not a real northbridge..
it's a hypertransport controller made by VIA to handle a bus of PCI express graphic card
SIS have the same this 'northbrige' architecture on its 755fx

hypertransport is free-royalty technology, and it is open technology, like linux world, anybody (vendors actually) can adopt its technology and give back some contribution on their development..
so, VIA marks their chips with 'HyperTransport Technology' inside, so is SIS..

 

[rgreen83]

I wasnt under the impression that the connection to the memory was a hypertransport bus, since hypertransport is serial and the mem interface is parallel, unless something similar to the sata-ata adaptors are built in, which would not be a good thing. I am now curious about this as well, I thought the increased performance from putting the mem controller on-die was just form decreased latency? The hypertransport is really the most useful in multi processor environments matched with NUMA communication between the cpus, as in opteron, allowing all cpus to have super fast access to each other and the system bus.

 

[Zebo]

All i care about is benchmarks. They can call it "quatum dilinear aquatic supported bus" and I still don't care. "Show me the ..numbers"

 

[batmanuel]

Originally posted by: incubus
maashass81..

maybe it's not a real northbridge..
it's a hypertransport controller made by VIA to handle a bus of PCI express graphic card
SIS have the same this 'northbrige' architecture on its 755fx

hypertransport is free-royalty technology, and it is open technology, like linux world, anybody (vendors actually) can adopt its technology and give back some contribution on their development..
so, VIA marks their chips with 'HyperTransport Technology' inside, so is SIS..

I think that VIA and SIS are using a two chip northbridge and southbridge solution purely for the cost savings using the same southbridge on a wide variety of chipsets. For example, the VIA VT8237 southbridge chip is used on most of their current P4, K7 and K8 chipsets - saving them a bundle in design and maufacturing costs. NVidia, on the other hand, uses a single chip solution because using a seperate southbridge wouldn't be of any benefit (as they can't at the moment legally make P4 chipsets and they have probably already manufactured just about all the K7 MCP chips that they'll ever need).

 

[sonoma1993]

I think hypertransport is just a fancy name for front side bus. from what I know, the hypertransports connects the cpu to the northbridge, then when you have a multiprocessor system, it connect each cpu,

 

[Viditor]

Originally posted by: hosto
What is better about hypertransport over a normal front side bus?

I mean, the hypertransport bus appears to run at 800mhz which is the same as the P4's 800mhz FSB

Hypertransport is a point to point connection instead of a common bus. This means that it doesn't "share".
That's why there are several HT connections within the design and why it's so much faster. There is also no chance of a bus conflict like there is with a common FSB...

 

[Sahakiel]

Originally posted by: sonoma1993
I think hypertransport is just a fancy name for front side bus. from what I know, the hypertransports connects the cpu to the northbridge, then when you have a multiprocessor system, it connect each cpu,

Athlon64's still have a traditional front side bus. Hypertransport is, in no way, capable of replacing the FSB. Not a single processor can interface directly with HyperTransport. Well, there might be a few niche players, but Intel, AMD, VIA, and Transmeta do not use HyperTransport as the FSB.
A FSB is simply the bus connection between the processor and the rest of the system. Traditionally, this has included the memory controller, other CPU's, and bus arbiters. Embedded systems were more likely to incorporate I/O devices on the FSB due to design constraints. The FSB moniker came about when caches were accessed using a separate back side bus. Nowadays, you don't hear about the back side bus because rising transistor budgets allowed integration of caches on die and/or caches are now placed in between processor and memory.
HyperTransport is a chip interconnect. It's serial for manufacturing and design reasons. Designs can use 8-bit or 16-bit links with varying clock speeds. HyperTransport is limited to two agents also for manufacturing and design reasons.
Athlon64's integrate the northbridge onto the processor die. The I/O bus is based on HyperTransport. MP capable chips have 2 or 3 HyperTransport buses, each of which can be used to link I/O devices or Opteron chips depending on the system design. Scalability with existing designs is limited to 8 Opterons before the system requires extra logic.

 

[Viditor]

Originally posted by: Sahakiel

Originally posted by: sonoma1993
I think hypertransport is just a fancy name for front side bus. from what I know, the hypertransports connects the cpu to the northbridge, then when you have a multiprocessor system, it connect each cpu,

Athlon64's still have a traditional front side bus. Hypertransport is, in no way, capable of replacing the FSB. Not a single processor can interface directly with HyperTransport. Well, there might be a few niche players, but Intel, AMD, VIA, and Transmeta do not use HyperTransport as the FSB.
A FSB is simply the bus connection between the processor and the rest of the system. Traditionally, this has included the memory controller, other CPU's, and bus arbiters. Embedded systems were more likely to incorporate I/O devices on the FSB due to design constraints. The FSB moniker came about when caches were accessed using a separate back side bus. Nowadays, you don't hear about the back side bus because rising transistor budgets allowed integration of caches on die and/or caches are now placed in between processor and memory.
HyperTransport is a chip interconnect. It's serial for manufacturing and design reasons. Designs can use 8-bit or 16-bit links with varying clock speeds. HyperTransport is limited to two agents also for manufacturing and design reasons.
Athlon64's integrate the northbridge onto the processor die. The I/O bus is based on HyperTransport. MP capable chips have 2 or 3 HyperTransport buses, each of which can be used to link I/O devices or Opteron chips depending on the system design. Scalability with existing designs is limited to 8 Opterons before the system requires extra logic.

I believe you are incorrect...
The A64 does not share a common FSB. Connections to other cores are via HT links, that's true...but connection to the Southbridge is ALSO via a HT link. In addition, data can flow in both directions simultaneously (unlike with a FSB). This is why the 800MHz is doubled to 1600 MHz on the documentation.

 

[Sahakiel]

Originally posted by: Viditor

Originally posted by: Sahakiel

Originally posted by: sonoma1993
I think hypertransport is just a fancy name for front side bus. from what I know, the hypertransports connects the cpu to the northbridge, then when you have a multiprocessor system, it connect each cpu,

Athlon64's still have a traditional front side bus. Hypertransport is, in no way, capable of replacing the FSB. Not a single processor can interface directly with HyperTransport. Well, there might be a few niche players, but Intel, AMD, VIA, and Transmeta do not use HyperTransport as the FSB.
A FSB is simply the bus connection between the processor and the rest of the system. Traditionally, this has included the memory controller, other CPU's, and bus arbiters. Embedded systems were more likely to incorporate I/O devices on the FSB due to design constraints. The FSB moniker came about when caches were accessed using a separate back side bus. Nowadays, you don't hear about the back side bus because rising transistor budgets allowed integration of caches on die and/or caches are now placed in between processor and memory.
HyperTransport is a chip interconnect. It's serial for manufacturing and design reasons. Designs can use 8-bit or 16-bit links with varying clock speeds. HyperTransport is limited to two agents also for manufacturing and design reasons.
Athlon64's integrate the northbridge onto the processor die. The I/O bus is based on HyperTransport. MP capable chips have 2 or 3 HyperTransport buses, each of which can be used to link I/O devices or Opteron chips depending on the system design. Scalability with existing designs is limited to 8 Opterons before the system requires extra logic.

I believe you are incorrect...
The A64 does not share a common FSB. Connections to other cores are via HT links, that's true...but connection to the Southbridge is ALSO via a HT link.

Uh... that's what I posted. Try reading before quoting.

In addition, data can flow in both directions simultaneously (unlike with a FSB). This is why the 800MHz is doubled to 1600 MHz on the documentation.

Bidirectional interconnects use two HyperTransport links, one in each direction. HyperTransport at it's simplest is a unidirectional 2-32 bit wide packet-based serial link. Current implementations on Athlon64 platforms use 8 and 16 bit iterations. Data cannot flow in both directions in a single HyperTransport link.