Should I try 1.7V? I already tried 200X10 at that. I could try 200X9 I guess and see if that is stable.
I read on TwinMos site that the DDR should be bumped up to 2.6V. I guess I should try that.
Double Data Rate architecture
MRS cycle with address key programs
*CAS latency: CL2, 2.5
*Burst length: 2, 4, 8
*Burst type: Sequential & Interleave
2 variations of refresh
*Auto refresh *Self refresh
Serial Presence Detect support
2 Banks to be operated simultaneously or independently
Package: TSOP/CSP
184 edge connector pads
Clock frequency: 133/166/200MHz
SSTL-2 interface: 2.6 Voltage +/- 0.2V
Review on TwinMos Suggesting higher voltage
I read on TwinMos site that the DDR should be bumped up to 2.6V. I guess I should try that.
Double Data Rate architecture
MRS cycle with address key programs
*CAS latency: CL2, 2.5
*Burst length: 2, 4, 8
*Burst type: Sequential & Interleave
2 variations of refresh
*Auto refresh *Self refresh
Serial Presence Detect support
2 Banks to be operated simultaneously or independently
Package: TSOP/CSP
184 edge connector pads
Clock frequency: 133/166/200MHz
SSTL-2 interface: 2.6 Voltage +/- 0.2V
Review on TwinMos Suggesting higher voltage
