What is Data Cache and Instruction Cache on a CPU?

[Regs]

I was reading the article on anandtech about the 3.2 Intel CPU's and noticed that the 3.2E Prescott has twice as much Data Cache as the others. What exactly is Data Cache and Instruction cache, and what's their function?

 

[Viper96720]

Lessen memory access

 

[Viper96720]

Lessen memory access L1 and L2

 

[Viper96720]

I just edited and it made a new reply strange

 

[buleyb]

The idea, is to keep data and instructions in fast cache memory that are used often. If they aren't used, they simple will get bumped out for more needed items. The more often you can simply reference things stored in L1 or L2 cache, the less of a performance hit you'll have, because you save the access to main memory.

This enough info for you?

 

[DaveSimmons]

www.ArsTechnica.com has CPU articles, but buleyb gives the basic explanation. Each level of cache is to keep data and upcoming code "close to hand" in faster storage than the next level, until finally it's stored on the hard drive.

 

[martind1]

wait a minute.

i think the cache might be to keep frequently used instructions close by for speed purposes.


wait ... has that been mentioned yet?😀

 

[Regs]

Originally posted by: martind1
wait a minute.

i think the cache might be to keep frequently used instructions close by for speed purposes.


wait ... has that been mentioned yet?😀

Yeap. Just wondering if it was any different then L1/L2/L3 cache. Thanks!

 

[aSnipingPenguin]

Originally posted by: Regs

Originally posted by: martind1
wait a minute.

i think the cache might be to keep frequently used instructions close by for speed purposes.


wait ... has that been mentioned yet?😀

Yeap. Just wondering if it was any different then L1/L2/L3 cache. Thanks!

Well, one of the principles that cache operates on is that smaller is faster, which is why the L1 caches are so small. Even so, something as big as a 1MB cache is still much faster than going to RAM, which is why we're seeing the advents of L2 and L3 caches as transistor densities increase.

But basically, instruction and data caches are considered together to be L1, though they're kept separate. It's like having two separate pages of notes for the two different things. Once you go to L2, L3 caches, though, I think most architectures start just throwing them into a general hodgepodge, like putting all of the less-used pages of notes into a binder off to the side.