What happened to AMD's C3 stepping?

[Idontcare]

There is a god, his name is Andrew Cuomo, and he is about to bless a slingshot.

Seriously though that is what will be the "great equalizer" in the long-term picture here...Intel can't help but fall victim, eventually, to anti-trust actions.

I don't say that based on assumptions of guilt on allegations of past actions but rather as a forward-looking synopsis of simple consequences of the math of the economics involved in the coming decade.

They've reached that kind of critical mass now where there is no stopping the ensuing chain reaction, it is simply a matter of time before the government agencies chartered with anti-trust issues find themselves with a political sentiment pendulum swung far enough in the "bust up big businesses" direction the likes of which AT&T and RCA found themselves.

The barrier to entry for advanced process tech has sealed Intel's fate by simple virtue of having the revenue necessary to procure continually advanced technology nodes on a node cadence that outstrips the competition and it is simply a matter of time before they get disassembled for sheer fact their competition will no longer be able to compete.

It's not a matter of beating the competition so much as the competition bowing out of the race, either way you end being the defacto monopoly in effect and eventually politics will decide you need disassembling to re-open the market space (look at deregulation, the stated motivations for it when it happens, and how it happens in ebbs and cycles based on political sentiment, the analog will happen to Intel IMO).

So I can't help but feel sorry for Intel because they could be the most saintly noble business out there who has been unfairly the victim of much false accusations and it won't change the fact they are a dead man walking when you iterate thru the next 10yrs and assess the ramifications of node cadence on product portfolio and R&D expenses and realize they are assured a monopoly position whether they want it or not and eventually government will be forced to address that.

So IMO AMD merely has to survive the duration and eventually government agencies will fight there fight for them and dismantle Intel limb by limb.

As for Bulldozer...I admit there is no good reason to assume it has any chance of besting Intel's architecture of the year whenever BD debuts. Consider that the K8 bested P4 prescot not so much because K8 was two steps ahead of K7 but because the P4 prescot was a step back from the P4 northwood...so unless Intel takes another step-back ala P4 prescot style we simply have no justification to put the odds in AMD's favor once we factor in the resource delta that exists between the two.

 

[jvroig]

Ouch. Now you've made me sad for Intel, not exactly what I was looking for when I was asking to be cheered up for AMD.

I have to admit, I didn't see that Intel chain reaction coming. I'm not from the U.S., and things like that have never happened here. When the NY AG antitrust lawsuit news broke, I just thought it would be yet another billion-dollar fine that Intel won't even miss and then back to business as usual.

 

[piesquared]

The Deneb and Shanghai architecture seems to have excellent power characteristics on their 45nm SOI process so maybe some are thinking of this whole thing in terms of nehalem and intel's 45nm process.( Also, from what i'm seeing,the nehalem architecture isn't going to scale down nearly as well as Core 2, so I bet AMD will have solid competition in performance/watt in low power products for sure). The ambient/cpu temp delta is huge with nehalem, so it kinda looks like they used up all it's potential with their current process; these things run HOT. It'll be interesting to see if they can scale up well on 32nm.

I bet we'll see very good performance/watt numbers from Thuban and Magny Cours, and probably see the real strong points of 45nm SOI. I also doubt if Intel could get a 12 core chip out and make much of a profit with it at 45nm. So the C3 stepping is just another improvement on an already stellar process.

 

[Fox5]

The Deneb and Shanghai architecture seems to have excellent power characteristics on their 45nm SOI process so maybe some are thinking of this whole thing in terms of nehalem and intel's 45nm process.( Also, from what i'm seeing,the nehalem architecture isn't going to scale down nearly as well as Core 2, so I bet AMD will have solid competition in performance/watt in low power products for sure). The ambient/cpu temp delta is huge with nehalem, so it kinda looks like they used up all it's potential with their current process; these things run HOT. It'll be interesting to see if they can scale up well on 32nm.

I bet we'll see very good performance/watt numbers from Thuban and Magny Cours, and probably see the real strong points of 45nm SOI. I also doubt if Intel could get a 12 core chip out and make much of a profit with it at 45nm. So the C3 stepping is just another improvement on an already stellar process.

I'm pretty sure in performance per watt, i7 beats both deneb and shanghai at load. It also beats them badly while idling.
And if AMD can slap two dies together and make a 12 core, why not intel?

Though I'm sure AMD's move to 32nm will be a bigger improvement than Intel's. They've got a lot more room to move up!

 

[Viditor]

I'm pretty sure in performance per watt, i7 beats both deneb and shanghai at load. It also beats them badly while idling.
And if AMD can slap two dies together and make a 12 core, why not intel?

Though I'm sure AMD's move to 32nm will be a bigger improvement than Intel's. They've got a lot more room to move up!

It is a misconception to think that an MCM is easy...
Can Intel do it? Of course they can...but that takes planning and design just like anything else (cache interactivity is a bitch for one thing). Creating an MCM (Multi-Core-Module) on today's CPU takes (at a guess) a good 2 years of work and a significant amount of money.

 

[piesquared]

[edit]

true

 

[Viditor]

Did you all see this?

FTC expected to take antitrust action against Intel


Clearly something Intel isn't looking forward to.

You should start a new thread...that's quite a bit off-topic mate...

 

[Fox5]

It is a misconception to think that an MCM is easy...
Can Intel do it? Of course they can...but that takes planning and design just like anything else (cache interactivity is a bitch for one thing). Creating an MCM (Multi-Core-Module) on today's CPU takes (at a guess) a good 2 years of work and a significant amount of money.

Intel seemed to do just fine with the Pentium D's and the Core 2's, and the Pentium D's seemed like a reaction to AMD's x2's.

 

[Hyperlite]

Intel seemed to do just fine with the Pentium D's and the Core 2's, and the Pentium D's seemed like a reaction to AMD's x2's.

But pentium D was a kneejerk reaction to the X2. 1 Prescott was bad enough...but two on the same die?! Core 2 debuted, architecturally, ahead of AMD. IIRC, that was about the time dell starting running some AMD proc's (after PD launch). Core 2 was natively multi-core, Pentium D wasn't. Clever and a bit lucky, maybe, as i don't think intel anticipated AMD going multicore so quickly.

 

[Viditor]

Intel seemed to do just fine with the Pentium D's and the Core 2's, and the Pentium D's seemed like a reaction to AMD's x2's.

I agree that the timings can be deceptive, but with Pent D, Intel was well aware of what was coming from AMD.
You can see the required timeframe of an MCM development in the fiasco of Barcelona though.
If creating an MCM was easy, then AMD would certainly have made one once they found out about Barcelona's problems. Price would not have been a major issue as they lost far more by not having a good quad core for quite a long time.
They even mentioned it as a mistake in their CC, and said that development would take too long and be too expensive to be worthwhile at that point. They fixed the design of their monolithic quad core instead...

 

[DrMrLordX]

Specifically regarding the IMC situation, my understanding was that the overwhelming majority of desktop apps are basically invariant to the memory bandwidth that today's dual-channel and triple-channel DDR2/DDR3 setups have to offer anyways. Will anyone actually find their AMD rig to be any faster with a new C3 stepping chip in it running DDR3-1333 instead of DDR3-1066?

If they can maintain the same memory timings when jumping from DDR3-1066 to DDR3-1333, then potentially yes. Remember, in many cases, it is not the memory bandwidth that is at issue; rather, it is the latency.

K10 takes about a 10% performance hit when it goes from a Deneb with 1 MB of L3 cache with around 40-60 cycle latency to a Propus with no L3 cache at all (forcing it to hit system memory with a latency of maybe 120-150 cycle latency or worse in the event that it can't find what it needs in the L2, not to speak of cache coherency issues). Reduce your memory latency and those cache misses stop hurting so much (as does the complete absence of L3 cache).

AMD really needs higher NB speeds and support for higher memory speeds and/or tighter timings to fully take advantage of their IMC, which, generally speaking, could achieve higher clock speeds on K8 chips than they can on K10 chips.

From what I can tell, while some of the AMD fanbois really wanted to see higher overall clock speeds, what many of them wanted to see were NB speeds in line with the 3.4+ ghz core speeds that K10 can currently generate on a decent air overclock. Imagine a $99 Propus chip OCed to 3.4 ghz with a 3.4 ghz NB and maybe 4-8 gigs of DDR3-1333 6-6-6-20? Or imagine a Deneb doing the same thing along with its 1 MB of L3 with 25-30 cycle latency? It wouldn't be an i5/i7 killer, but it would be an improvement.

It really wouldn't make K10 chips any faster, as we all know . . . it would merely reduce the chances of K10s getting bogged down by slow-ass memory/L3 cache.

 

[heyheybooboo]

My point exactly. The review sites seem more interested in the overclockability of the C3 stepping than in the fix that has plauged the AMD IMC design since it was released.

My S939 4800 X2 took a big performance hit once I upgraded from 2 X 1MB to 4 X 1MB.

Since the 965BE that I just got still has the same problem, I figured that I would wait to increase the CPU speed until I got around to filling all 4 of my memory slots. An attempt to offset the performance hit of the down clocking the memory.

I haven't been paying a great deal of attention as of late but the folks at XS seem to be on the bleeding edge of performance with the AMD memory controller.

They are now breaking 3000MHz with the IMC/NB --- I'm guessing this is with 'C3' but don't really know.

The advantage is that for each 10% increase in IMC/NB speed, memory bandwidth is increased 3-4% and latency is reduced 3-4%.

The issue heretofore has been the loss of 'dual-channel' with the use of 4 DIMMs. I'm not really sure where C3 stands with this but I'm encouraged by the likelihood that IMC tweaks have further improved high-end performance for those who actually need the increased bandwidth and reduced latency.

It more than compensates for the loss of dual-channel, or, speed reduction from, let's say, 1600MHz to 1333MHz.

Back to the XS Guys: Last time I passed through there they were getting those great IMC/NB numbers and tweaking their timings really low more than compensating for ... the performance hit of the down clocking the memory. .

 

[DrMrLordX]

They are now breaking 3000MHz with the IMC/NB --- I'm guessing this is with 'C3' but don't really know.

From what I understand, a few folks over at AMDzone have hit similar NB speeds on air with C2 chips. The amount of information out there on C3's NB speed potential seems a bit lacking with "it varies from chip to chip" being the official line you'll get from most AMD fans.

The advantage is that for each 10% increase in IMC/NB speed, memory bandwidth is increased 3-4% and latency is reduced 3-4%.

Don't forget that, when it comes to Deneb chips (and other chips with L3), L3 cache latency is reduced as well.