What ever happened to electron tunneling?

[cheesehead]

A while back, everyone was up in arms about CPU design and the use of silicon. Cores were getting progressively smaller, and everyone was worried that they would'nt get much smaller than they already were.
Now, Intel is hitting 65nm with no problems, and lower voltages than ever. 45nm CPU's are in the works, too.

Now, I always thought that at 45nm and below, a CPU would'nt work properly. How is Intel able to do this? Are they going to simply run the CPU's at higher voltages?

 

[Eeezee]

I'm not sure at what distances electron tunneling becomes a serious problem, but I would guess this means that CPU architecture just hasn't reached the limit yet (but is approaching it)

 

[CTho9305]

If you keep the gate oxide thicker, tunnelling becomes less of a problem (but your transistors get slower).

 

[SergeC]

I believe different doping techniques, and different substrate materials, have quite a bit to do with the pushing back of the previously-labelled "limits"

 

[pm]

Tunnelling is still a major battle. It is more commonly referred to as "leakage" but the two main forms of leakage on 65nm, gate leakage and subthreshold leakage, are basically a form of tunnelling.

People have worked around the leakage to some extent (the use of lower-than-the-rest-of-the-die voltages for cache, reduction of on-die gate-based decoupling capacitors, sleep transistors). The two big levers for reducing gate leakage are larger gate dielectic thicknesses, larger gate dielectric constants, and reducing the voltage. The problem with all of these approaches is that they slow down the transistor's operation. So power is a function of transistor switchign speed. You can reduce power but everything slows down.

If you look objectively at the industry, transistor speed should have been holding constant from 90nm to 65nm... except that everyone is adopting strained silicon techniques - which is a bit like changing the game.

 

[cheesehead]

Interesting.
I would wonder if AMD is going to more aggressively clock their chips when they hit 65nm. Although they're currently playing "catch-up" to Intel, I would not be surprised if they were able to take advantage of more refined 65nm processes. Or, perhaps they're skipping to 45nm; although it might make for slower CPUs, it would mean that you could cram twice as many CPU's on to a die compared to their competitors, allowing them to drop costs or more efficiently make multiple-core processors.
As an added bonus, these low-voltage chips would also take far less power than most modern CPU's. An AMD Sempron at 1.4 ghz is all that is needed for most of my customers, and if they could produce them for 40$ each, they would quickly be the processor of choice for low-end PC's. Combine this with a cheap chipset (remember, it has a built-in memory controller!) and you've got a way to produce 150$ PC's.

 

[Hyperlite]

Originally posted by: Cheesehead
Interesting.
I would wonder if AMD is going to more aggressively clock their chips when they hit 65nm. Although they're currently playing "catch-up" to Intel, I would not be surprised if they were able to take advantage of more refined 65nm processes. Or, perhaps they're skipping to 45nm; although it might make for slower CPUs, it would mean that you could cram twice as many CPU's on to a die compared to their competitors, allowing them to drop costs or more efficiently make multiple-core processors.
As an added bonus, these low-voltage chips would also take far less power than most modern CPU's. An AMD Sempron at 1.4 ghz is all that is needed for most of my customers, and if they could produce them for 40$ each, they would quickly be the processor of choice for low-end PC's. Combine this with a cheap chipset (remember, it has a built-in memory controller!) and you've got a way to produce 150$ PC's.

So is it intentional (becuase of tunneling) or just coincidental that IPC is increasing? isn't this at least a temporary workaround? processors, in general, are not getting much faster (if at all) but IPC is definantly increasing.

Die skrinks>lower transistor speed>increased IPC

They all go together, and not just for thermal reasons.

 

[CTho9305]

I would wonder if AMD is going to more aggressively clock their chips when they hit 65nm. Although they're currently playing "catch-up" to Intel, I would not be surprised if they were able to take advantage of more refined 65nm processes. Or, perhaps they're skipping to 45nm; although it might make for slower CPUs, it would mean that you could cram twice as many CPU's on to a die compared to their competitors, allowing them to drop costs or more efficiently make multiple-core processors.

At the 2006 Technology Analyst Day, a presentation discusses 65nm (slide 33, for example). Anandtech also has an article with all the interesting bits from a bunch of presentations.

edit: Here is probably a pretty good list of the presentations if you want to read them yourself. Slide 10 here has a picture captioned, "High-performance, power-efficient 65nm AMD64 processors on 300mm production wafer".

 

[jackwhitter]

intel is continually decreasing voltage. electron tunnelling and/or dielectric breakdown occurs when the voltage is high enough to cause the electron to jump over/tunnel through the insulation. by decreasing voltage and increasing gate dielectric they can decrease physical sizes. also, ati is starting to use negative biased gating when the gate is "off." not sure if intel or anyone else is using this technique.

 

[f95toli]

It is worth remembering that the tunnelling probability of an electron is related to the ELECTRIC POTENTIAL the electron "sees", NOT the distance it need to tunnel "to get to the other side".
Hence, the dimensions of the device are not direcly relevant.
However, of course it becomes more difficult to control the potential as the dimensions become smaller, but by using other materials you can in principle keep the tunnlling current small which I guess is what Intel and AMD is doing.

Btw, there is no such thing as tunnelling OVER a potential. The latter process is called thermal activation and is a classical process where the electron is basically "kicked" over the barrier.