Originally posted by: Wicked2010
The registers on the CPU will now be 64-bits. Meaning, you can push around twice the amount of data than before. So basically the bandwidth is doubled. Think of it as a highway. If you had 32 lanes for traffic before, you are definitely going to get more cars down the highway with 64 lanes instead.
And as you said, you can now address more memory. Before we could address up to 4 GB of memory... with 64 bits it will now be 17179869184 GB of memory. Which will last until the year 3000 probably... lol. Although 128 bit will come someday just to increase bandwidth.
That's it!!
Originally posted by: Wicked2010
Even if it's 33 bit instead of 32 bit, then we now have at least 8 GB of addressable space. It keeps doubling for each bit you add.
We clearly won't need all 64 bits until ... well.. possibly never.
Originally posted by: Wicked2010
The registers on the CPU will now be 64-bits. Meaning, you can push around twice the amount of data than before. So basically the bandwidth is doubled. Think of it as a highway. If you had 32 lanes for traffic before, you are definitely going to get more cars down the highway with 64 lanes instead.
Originally posted by: kylef
Originally posted by: Wicked2010
The registers on the CPU will now be 64-bits. Meaning, you can push around twice the amount of data than before. So basically the bandwidth is doubled. Think of it as a highway. If you had 32 lanes for traffic before, you are definitely going to get more cars down the highway with 64 lanes instead.
This is very, very misleading. Please do not spread statements like this, because it simply promotes more 64-bit ignorance.
Increasing register size from 32-bit to 64-bit has virtually no effect on I/O performance as you are claiming. If programs simply shuffled data around in registers with the goal being to maximize the amount of data transferred, you would be correct. But the vast majority of programs do not work this way!
Think about a simple operation like this (adding two numbers together):
load r1, @r3 # a = value1
load r2, @r4 # b = value2
addu r1, r1, r2 # a = a + b
For these instructions, you have gained *nothing* by moving from 32-bit to 64-bit. This takes exactly the same amount of time to execute on a 32-bit platform as a 64-bit platform for ALL values that can be stored in a 32-bit register. The ONLY case where the 64-bit platform is faster is for values of a and b that cannot be stored in 32-bits (i.e., greater than 4 billion). But that is a very uncommon case.
Actually, the above code will usually execute SLOWER on the 64-bit platform because the code size has increased to handle 64-bit pointers and registers. On AMD64, the average instruction length for 64-bit instructions has increased by roughly 0.7 bytes. This extra overhead accomplishes nothing for most data sets, and causes two serious performance hits: 1) the instruction cache is less effective (its capacity is reduced, and locality has decreased) and 2) page fault probability has increased.
The ONLY factor that offsets this increase in average instruction length for the AMD64 instruction set is that the total instruction count for AMD64 programs is smaller than that for IA32, because the extra 8 general purpose registers available to 64-bit instructions allows compilers to generate fewer register load/stores (more storage for temporaries).
Originally posted by: Duvie
Originally posted by: kylef
Originally posted by: Wicked2010
The registers on the CPU will now be 64-bits. Meaning, you can push around twice the amount of data than before. So basically the bandwidth is doubled. Think of it as a highway. If you had 32 lanes for traffic before, you are definitely going to get more cars down the highway with 64 lanes instead.
This is very, very misleading. Please do not spread statements like this, because it simply promotes more 64-bit ignorance.
Increasing register size from 32-bit to 64-bit has virtually no effect on I/O performance as you are claiming. If programs simply shuffled data around in registers with the goal being to maximize the amount of data transferred, you would be correct. But the vast majority of programs do not work this way!
Think about a simple operation like this (adding two numbers together):
load r1, @r3 # a = value1
load r2, @r4 # b = value2
addu r1, r1, r2 # a = a + b
For these instructions, you have gained *nothing* by moving from 32-bit to 64-bit. This takes exactly the same amount of time to execute on a 32-bit platform as a 64-bit platform for ALL values that can be stored in a 32-bit register. The ONLY case where the 64-bit platform is faster is for values of a and b that cannot be stored in 32-bits (i.e., greater than 4 billion). But that is a very uncommon case.
Actually, the above code will usually execute SLOWER on the 64-bit platform because the code size has increased to handle 64-bit pointers and registers. On AMD64, the average instruction length for 64-bit instructions has increased by roughly 0.7 bytes. This extra overhead accomplishes nothing for most data sets, and causes two serious performance hits: 1) the instruction cache is less effective (its capacity is reduced, and locality has decreased) and 2) page fault probability has increased.
The ONLY factor that offsets this increase in average instruction length for the AMD64 instruction set is that the total instruction count for AMD64 programs is smaller than that for IA32, because the extra 8 general purpose registers available to 64-bit instructions allows compilers to generate fewer register load/stores (more storage for temporaries).
Good read!!!
By the way what are those "uncommon cases".....It appears that graphics intensive apps like complex 3d rendering have a bit of an increase...can you explain how this is....
That is the area I am more likely to need in a 64bit environment...otherwise there is not much of a need for me to change OSes
Originally posted by: Jeff7181
Originally posted by: Duvie
Originally posted by: kylef
Originally posted by: Wicked2010
The registers on the CPU will now be 64-bits. Meaning, you can push around twice the amount of data than before. So basically the bandwidth is doubled. Think of it as a highway. If you had 32 lanes for traffic before, you are definitely going to get more cars down the highway with 64 lanes instead.
This is very, very misleading. Please do not spread statements like this, because it simply promotes more 64-bit ignorance.
Increasing register size from 32-bit to 64-bit has virtually no effect on I/O performance as you are claiming. If programs simply shuffled data around in registers with the goal being to maximize the amount of data transferred, you would be correct. But the vast majority of programs do not work this way!
Think about a simple operation like this (adding two numbers together):
load r1, @r3 # a = value1
load r2, @r4 # b = value2
addu r1, r1, r2 # a = a + b
For these instructions, you have gained *nothing* by moving from 32-bit to 64-bit. This takes exactly the same amount of time to execute on a 32-bit platform as a 64-bit platform for ALL values that can be stored in a 32-bit register. The ONLY case where the 64-bit platform is faster is for values of a and b that cannot be stored in 32-bits (i.e., greater than 4 billion). But that is a very uncommon case.
Actually, the above code will usually execute SLOWER on the 64-bit platform because the code size has increased to handle 64-bit pointers and registers. On AMD64, the average instruction length for 64-bit instructions has increased by roughly 0.7 bytes. This extra overhead accomplishes nothing for most data sets, and causes two serious performance hits: 1) the instruction cache is less effective (its capacity is reduced, and locality has decreased) and 2) page fault probability has increased.
The ONLY factor that offsets this increase in average instruction length for the AMD64 instruction set is that the total instruction count for AMD64 programs is smaller than that for IA32, because the extra 8 general purpose registers available to 64-bit instructions allows compilers to generate fewer register load/stores (more storage for temporaries).
Good read!!!
By the way what are those "uncommon cases".....It appears that graphics intensive apps like complex 3d rendering have a bit of an increase...can you explain how this is....
That is the area I am more likely to need in a 64bit environment...otherwise there is not much of a need for me to change OSes
It's not the size of the GPR's, it's the amount. There's twice as many GPR's available in 64-bit mode. The GPR's being 64-bits wide rather than 32 only allows larger numbers (integers) to be used, which is almost useless at this point.
*Edited for clarity*
**EDIT** I think the floating point units in processors have been 64-bits wide for some time now... haven't they?
Originally posted by: Duvie
Originally posted by: Jeff7181
Originally posted by: Duvie
Originally posted by: kylef
Originally posted by: Wicked2010
The registers on the CPU will now be 64-bits. Meaning, you can push around twice the amount of data than before. So basically the bandwidth is doubled. Think of it as a highway. If you had 32 lanes for traffic before, you are definitely going to get more cars down the highway with 64 lanes instead.
This is very, very misleading. Please do not spread statements like this, because it simply promotes more 64-bit ignorance.
Increasing register size from 32-bit to 64-bit has virtually no effect on I/O performance as you are claiming. If programs simply shuffled data around in registers with the goal being to maximize the amount of data transferred, you would be correct. But the vast majority of programs do not work this way!
Think about a simple operation like this (adding two numbers together):
load r1, @r3 # a = value1
load r2, @r4 # b = value2
addu r1, r1, r2 # a = a + b
For these instructions, you have gained *nothing* by moving from 32-bit to 64-bit. This takes exactly the same amount of time to execute on a 32-bit platform as a 64-bit platform for ALL values that can be stored in a 32-bit register. The ONLY case where the 64-bit platform is faster is for values of a and b that cannot be stored in 32-bits (i.e., greater than 4 billion). But that is a very uncommon case.
Actually, the above code will usually execute SLOWER on the 64-bit platform because the code size has increased to handle 64-bit pointers and registers. On AMD64, the average instruction length for 64-bit instructions has increased by roughly 0.7 bytes. This extra overhead accomplishes nothing for most data sets, and causes two serious performance hits: 1) the instruction cache is less effective (its capacity is reduced, and locality has decreased) and 2) page fault probability has increased.
The ONLY factor that offsets this increase in average instruction length for the AMD64 instruction set is that the total instruction count for AMD64 programs is smaller than that for IA32, because the extra 8 general purpose registers available to 64-bit instructions allows compilers to generate fewer register load/stores (more storage for temporaries).
Good read!!!
By the way what are those "uncommon cases".....It appears that graphics intensive apps like complex 3d rendering have a bit of an increase...can you explain how this is....
That is the area I am more likely to need in a 64bit environment...otherwise there is not much of a need for me to change OSes
It's not the size of the GPR's, it's the amount. There's twice as many GPR's available in 64-bit mode. The GPR's being 64-bits wide rather than 32 only allows larger numbers (integers) to be used, which is almost useless at this point.
*Edited for clarity*
**EDIT** I think the floating point units in processors have been 64-bits wide for some time now... haven't they?
How is it useless if I am seeing programs like I mentioned running a bit faster???
Well first of all, you always want to compare two identical platforms: one running 32-bit and one running 64-bit. But comparing identical platforms is VERY complicated.Originally posted by: Duvie
By the way what are those "uncommon cases".....It appears that graphics intensive apps like complex 3d rendering have a bit of an increase...can you explain how this is....
Correct, and those should help compilers generate faster floating-point code. But again, those should only be factored in when comparing SSE-enabled 32-bit apps to SSE-enabled 64-bit apps.Originally posted by: bersl2
In addition to 8 more GPRs, there are also 8 more SSE registers too.
Originally posted by: VirtualLarry
So considering both together, I think one might somewhat make up for the other, and when using the extra 8 GPRs, but still using more cache-efficient 32-bit operand sizes, you would get the best of both worlds.
Yep, I would agree with that. I think they should consider increasing the L1 instruction cache size. (From my recollection of "cache architecture 101" in grad school, extra unified L2 cache doesn't really help instruction execution that much). But I'm sure that their cache designers are experimenting with all sorts of configurations, and anything we can come up with has probably already been tried. If they need to squeeze more performance out of their cache architecture, I'm sure they can. (AMD is still the only company mass producing an orthogonal L2 cache on their CPUs from what I understand: Intel still uses the traditional hierarchical type I believe. And NUMA is a pretty radical change over SMP. So AMD has a history of trying some unusal architectures in an attempt to improve performance. Granted, they aren't the first to come up with these ideas, but they may be the first to re-examine them in quite some time.)I am slightly disturbed at how more recent AMD64 chips are being released with smaller L2 cache sizes, because once actual 64-bit code starts to arrive, users are going to see the real performance benefit from those larger cache sizes.