No it won't.
Even if silicon wafer costs 10k for N7 process, and for 16/14 nm process wafers cost 6500, that leaves you with 11$ per die, in best case scenario for IO die made on 14 nm process.
Whats funnier, only 400 mm2 monolithic die made on N7 process, wil equal manufacturing costs of seperate IO die, CPU and GPU chiplets.
And here comes the design costs. You pay for one design. Not three speparate.
AMD decided to go with chiplet based design, because its cheaper to design and manufacture ONLY FOR CPUs. Even their own 7 nm APUs, based on Zen 2 architecture, for desktop computers, will be completely monolithic, and not Chiplet based.
If N7 wafers cost 10k, 400 mm2 die costs 71$ to yield. 255 mm2 die costs 44$, if N7 wafers cost 10 grand. In the best case scenario, obviously. 350 mm2 die, which is more in line with the die size of previous consoles die sizes, will cost 60-65$ depending on Yield on N7.
1] This technique is not only applicable to CPUs, but to many SOCs.
2] All the die yield equations have an exponential component, and real world data confirms it.
As an example:
http://www.isine.com/resources/die-yield-calculator
400mm^2 chiplet based on (2) 200mm^2 chiplets versus a 375mm^2 SOC. I assume some extra space for communicating.
Defect density = 0.2 (any yield rate gives a discrepancy)
Chiplet = 14.1mm * 14.1mm gives 192 good die/wafer with a 68.1% yield
SOC = 19.4mm * 19.4mm gives 69 good die/wafer with a 49.4% yield
You end up with 96 (192/2) chiplet based units versus 69 SOC units. A 39% increase in good die/wafer or a cost of 72% of the full SOC.
3] Speculating on the wafer price is irrelevant as it applies to both cases.
4] Perhaps (most likely), the 7nm APU coming will only have 4C/8T and the Zen chiplet will be wasted in discarding 1/2 the cores. As I expected to happen, we already do not see any 4C Matisse, but the consoles will have 8C, so it can be used there. Zen3 will also be on 7nm+.
I think that the IO will be on the GPU portion of the die leading to 2 chiplets. The GPU will have greater data traffic and you would want to reduce distances for power consumption savings. This will lead to only 1 new design/console. Sony and Microsoft, each with their unique custom components in the GPU chiplet.
Edit: using more realistic sizes for die.
CPU chiplet = 75mm^2 (7.5 X 10.0)
GPU/IO chiplet =275mm^2 (14.36 x 19.15)
Unified SOC =350 mm^2 (16.2 x21.6)
Chiplet = 676 die @ Y 85.9%
GPU/IO chiplet = 117 die @ Y 59.2
SOC = 79 die @ Y 51.7
It takes 5.78 wafer of GPU/IO to mate with 1 wafer of CPU
So 6.78 wafer gives you 676 chiplet based console units.
But 6.78 wafers gives you only 536 SOC units.
You will spend 26% more to fab the SOC. Taking your $60 cost/SOC, this is ~ $1.5B over the console lifetime @ 100M units sold. Not a trivial amount.
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