Vishera Review Up - Anandtech

[inf64]

Yeah it's not a conventional 8 core,more like a quasi 8 core with SMT in the FPU. That's why it "only" competes with QC i7 with SMT in MTed SSE workloads, there simply are not that many execution units per core for it to do more. 4 FP units with MTing is a tradeoff AMD opted for in order to "squeeze" 8 integer cores for some server workloads they designed it for. All in all it does compete, albeit with higher power draw.

 

[Idontcare]

i think that you missed the part, that there is no Clock Mesh on Vishera...just on trinity

The clockmesh is on both, it just isn't enabled/used on Vishera because the clock targets of Vishera are outside the optimal window.

AMD implemented both conventional and resonant clock mesh on piledriver, you can't remove it would undoing years of co-optimization work on piledriver which would then set off another year's worth of validation work.

Resonant mesh is present on the Vishera die, AMD may have disabled it so that Vishera doesn't take advantage of it, but let us be clear that there is a difference in these statements.

I am not surprised to hear Vishera doesn't use the resonant mesh, the target clocks are simply way too high.

I would also be surpised if steamroller uses resonant mesh. The window of opportunity for the resonant mesh is just too narrow to justify the effort and expense relative to the minor power-reduction benefit.

 

[The Alias]

I would like to see an 8350 review with 1 core per module disabled

 

[AtenRa]

And your computer will spend very little time actually at full load (even less for the FX than for the i5, as it gets the job done quicker ).

He knows that, he choose to only post the graph that will make the competition look the baddest. I can do the same,

faster than 3770K costing 50% less

 

[Olikan]

AMD implemented both conventional and resonant clock mesh on piledriver, you can't remove it would undoing years of co-optimization work on piledriver which would then set off another year's worth of validation work.

mmm...i thought that it was easyer to set a "target clocks" :thumbsup:

Well, RCM might explains why no trinity can't past 4.6Ghz, while some vishera reach 5.1 Ghz

 

[Idontcare]

mmm...i thought that it was easyer to set a "target clocks" :thumbsup:

Well, RCM might explains why no trinity can't past 4.6Ghz, while some vishera reach 5.1 Ghz

Target clocks are set by physically sizing the inductors accordingly. The middle part of the whitepaper spend a fair amount of time discussing the layout aspects.

It is just one of those things that are an incremental improvement but in no way does it meet the expectations that are generated by certain marketing aspirations at first blush.

I felt the same level of "that's it? meh" over Intel's clamor to make sure everyone knew they migrated from dynamic to static CMOS logic with Nehalem. Then we got the chips in the public domain and found power-consumption really didn't decrease as much as we were led to expect. Resonant mesh kinda worked out that way too. It helps but not by much.

 

[Olikan]

I felt the same level of "that's it? meh" over Intel's clamor to make sure everyone knew they migrated from dynamic to static CMOS logic with Nehalem. Then we got the chips in the public domain and found power-consumption really didn't decrease as much as we were led to expect. Resonant mesh kinda worked out that way too. It helps but not by much.

yep, i just wanted to point out that vishera power consumtion is based on the metal re-spin...not the RCM

IMO, we will need a fx-4300 and a trinity with igp disabled to have a fair idea to what the RCM really brings...

 

[podspi]

I wish there was a toggle so we could see how much it helps in reality. Trinity's clock speed (turbo) is much higher than Llano's. A lot of power is used not in idle (where power use is low anyway) but during burst workloads. Lowering the power used during burst loads (which for mobile trinity will probably be around that 3ghzish clockspeed) could be quite useful.

Or not, dunno.

IMO, we will need a fx-4300 and a trinity with igp disabled to have a fair idea to what the RCM really brings...

Yep, although controlling for platform might be difficult. IDC, can you set the 'target' clock for RCM, or is it set to the technology?

 

[Idontcare]

I wish there was a toggle so we could see how much it helps in reality. Trinity's clock speed (turbo) is much higher than Llano's. A lot of power is used not in idle (where power use is low anyway) but during burst workloads. Lowering the power used during burst loads (which for mobile trinity will probably be around that 3ghzish clockspeed) could be quite useful.

Or not, dunno.



Yep, although controlling for platform might be difficult. IDC, can you set the 'target' clock for RCM, or is it set to the technology?

It is set by the design itself, baked in so to speak, just like cache size. You can't waltz into piledriver and just double the L1$ for example, it don't work like that.

But I think folks might still be missing the value of the AMD whitepaper, they did exactly what you guys are looking for. They toggled the conventional versus resonant modes with piledriver silicon. It wasn't a test chip, it wasn't simulated. And they showed the reality of what it brings.

At best all we'd be doing is duplicating their results, and since the results already come from AMD I am inclined to believe that the numbers AMD published are likely to be best case scenarios as is. We aren't going to find an even rosier picture duplicating their tests IMO.

 

[SunnyD]

The clockmesh is on both, it just isn't enabled/used on Vishera because the clock targets of Vishera are outside the optimal window.

AMD implemented both conventional and resonant clock mesh on piledriver, you can't remove it would undoing years of co-optimization work on piledriver which would then set off another year's worth of validation work.

Resonant mesh is present on the Vishera die, AMD may have disabled it so that Vishera doesn't take advantage of it, but let us be clear that there is a difference in these statements.

I am not surprised to hear Vishera doesn't use the resonant mesh, the target clocks are simply way too high.

I would also be surpised if steamroller uses resonant mesh. The window of opportunity for the resonant mesh is just too narrow to justify the effort and expense relative to the minor power-reduction benefit.

Here's an interesting thought - could it be possible for AMD to put in a "low power state" into Vishra where the CPU downclocks into an optimal range and enables the resonant mesh for the additional power savings? I wonder what the combination of lower clock and turning on the feature would put power consumption at. (Probably should just look at Trinity for that I guess)

 

[CTho9305]

It is set by the design itself, baked in so to speak, just like cache size. You can't waltz into piledriver and just double the L1$ for example, it don't work like that.

But I think folks might still be missing the value of the AMD whitepaper, they did exactly what you guys are looking for. They toggled the conventional versus resonant modes with piledriver silicon. It wasn't a test chip, it wasn't simulated. And they showed the reality of what it brings.

At best all we'd be doing is duplicating their results, and since the results already come from AMD I am inclined to believe that the numbers AMD published are likely to be best case scenarios as is. We aren't going to find an even rosier picture duplicating their tests IMO.

I got the impression that all data in the paper was from simulations rather than silicon. Did they state it somewhere? Also, if it can turn the resonant functionality on/off at different frequencies, that pretty much guarantees that the cutoff point is controlled by a (hidden?) MSR. Maybe a BIOS can enable/disable it or change the cutoff. Anand should ask whether there's a way to do the comparison. It'd be very interesting to see data from someone who isn't making a sales pitch!

 

[Idontcare]

I got the impression that all data in the paper was from simulations rather than silicon. Did they state it somewhere? Also, if it can turn the resonant functionality on/off at different frequencies, that pretty much guarantees that the cutoff point is controlled by a (hidden?) MSR. Maybe a BIOS can enable/disable it or change the cutoff. Anand should ask whether there's a way to do the comparison. It'd be very interesting to see data from someone who isn't making a sales pitch!

They make multiple references to "measurements" in the paper which I just assumed meant they were measured, not simulated measurements. Do they do that? I must admit I don't know enough to say they wouldn't.

But if you look through the paper at all the traces, they don't look simulated, it all looks like measured data on the traces.

For example, slide 31 has a graph that is titled "Measured Efficiency (%) vs. Frequency", I would expect them to title that as "Modeled Efficiency..." or "Simulated Efficiency..." if it wasn't actually measured per se.

And on slide 32, the graph with the fmax results. The presence of error bars, and outliers below 3.4GHz for the resonant clock samples, suggests to me that is intended to represent measured data on real samples and not a simulated estimation of the fmax distribution.

Do you see it that way? What am I missing?

 

[frozentundra123456]

He knows that, he choose to only post the graph that will make the competition look the baddest. I can do the same,

faster than 3770K costing 50% less

Lets quit all the BSing about energy use. According to Toms hardware the two ivy cpus used an average of 225 watt-hours to finish the complete benchmark suite that includes the multi-threaded apps that AMD fans love so much. The 8350 took 352 watt-hours.

So there is no doubt intel accomplishes x amount of work with less power, cherry picked benchmarks aside. How important that is to you is up to the individual. Personally to me it is rather important since the time taken to completion is not nearly as much different as the power usage.

 

[sequoia464]

yep, i just wanted to point out that vishera power consumtion is based on the metal re-spin...not the RCM

Thanks for bringing this up, I have seen this mentioned a few times but this is the first discussion I have seen on the RCM and how it pertains to vishera.

 

[Shamrock]

I wonder if I can take my Phenom II apart, and solder my IPC onto a new FX-8350?

 

[Olikan]

I wonder if I can take my Phenom II apart, and solder my IPC onto a new FX-8350?

you can always buy a fx-8350, disable one core of each module and enjoy a +15 higher IPC than PhenomII

doing that probably reduces the power consuption by alot too (and might overclock better)

 

[podspi]

you can always buy a fx-8350, disable one core of each module and enjoy a +15 higher IPC than PhenomII

doing that probably reduces the power consuption by alot too (and might overclock better)

Does singlethread performance really increase by that much when disabling one module? (If you are only using one thread, I mean)

 

[Abwx]

OEM dedicated CPUs on sight.....

[FX-8300 et FX-6350, mais aussi un Zambezi Bulldozer : le FX-8140

Use Gtranslate...

http://www.comptoir-hardware.com/ac...-et-meme-fx-8140-debarquent-chez-les-oem.html

 

[sequoia464]

OEM dedicated CPUs on sight.....



Use Gtranslate...

http://www.comptoir-hardware.com/ac...-et-meme-fx-8140-debarquent-chez-les-oem.html

Thanks

That 8300 looks interesting.

Took a couple of years of French back in High School - 60's - so I have managed to loose most of the sparse comprehension that I had even in the best of times. One thing that I did understand without any doubt was the "bullshit" comment from the second poster. Looks like some words and phrases are universal. Don't know what the argument was, but we do know that someone is full of it.

 

[Olikan]

Does singlethread performance really increase by that much when disabling one module? (If you are only using one thread, I mean)

yes, around 20%

read here:
http://www.extremetech.com/computing/138394-amds-fx-8350-analyzed-does-piledriver-deliver-where-bulldozer-fell-short/2

 

[SocketF]

Old post, but I saw it just now, and thought to give some comments:

Resonant mesh is present on the Vishera die, AMD may have disabled it so that Vishera doesn't take advantage of it, but let us be clear that there is a difference in these statements

If it would be have been disabled, then how would the clock signals be distributed?

I'd say that there is nothing of RCM in Vishera and that the AMD contact of Planet3dnow.de says the truth. You know yourself that the RCM is useless for a high-clock processor, then wouldn't it be the best solution to not to use it in the FX-CPUs that should clock higher than Trinity? I don't think that AMD's engineers are that stupid. Furthermore, from the whitepaper that you linked you can see that the RCM uses square inductors that are visible in the die-shot. However, with the Vishera-die-shot (source)) you cannot see these squared structures:
Link:
http://www.abload.de/image.php?img=piledrvier_inductorsnps4v.png

To sum it up:

a) Why would the AMD contact lie in that matter? They'd normally lie telling you that the product has all of the super duper features, but normally won't tell you that sth. is missing.
b) Assuming that Vishera has both - a RCM and a normal Clock-Grid and that the RCM is disabled is not reasonable.
c) If RCM is not beneficial at high clock speeds, then why would AMD's engineers use it for a high-clock chip?
d) There are no inductors visible in the Vishera die-shot.

Conclusion:
There is no RCM@Vishera.