"Video BIOS Shadow" Enable or Disable?

[RideFree]

You'll never guess which setting it has in the BIOS!? One guess, that's all you get.

OK! Here goes...
"Wax on! Wax off!"?




(You're right, this has been one heckofa thread. Thanks everyone!)

 

[RideFree]

BTW teqwiz,

I'll be expecting to see some newz about that "Dragon blowing the doors off of that Epox" 8K5A2+ in the thread that's pinned in the number one slot on this forum. AllRight!

 

[KF]

That quote claiming you would waste cache space on the video BIOS was incredible.

Thanks to Peter, if he hasn't been thanked enough, for the first genuinely informative comments on this subject I have ever read.

Like a lot of people who have tried to fix mysterious glitches, I have fooled with these settings countless times just to exhaust every possiblity, because they are mentioned by every video card maker and mentioned in every FAQ. I have never found it to fix anything, (or to hurt anything) which actually is a bit mysterious considering there is such a setting. It looks like people are just trying to cover all the bases, because no one really knows.

I have also wondered how it is possible to execute code over the PCI bus, considering the way PCI is described, and I think I understand now that it IS impossible to do directly.

 

[Peter]

Oh yes, one can execute code over the PCI bus just as well as you can load and store data. You just don't get a ROM on the PCI bus to appear in the legacy expansion ROM space at 0xC0000..0xEFFFF, where it must be to function as an expansion to BIOS POST as we know it. Put 32-bit protected mode code into such a ROM, call it from a 32-bit operating system, and you're set. But BIOS POST runs in miserable 16-bitty IBM XT compatible legacy mode with one megabyte of address space, so your card's BIOSes _must_ appear in said region ... and the only way to make that happen is to send system BIOS into 32-bit address space mode briefly, copy the ROM content from the PCI device into system RAM in the "right" spot below the 1 MByte border (which would otherwise be wasted anyway), return to miserable 16-bit mode, and invoke the copy in RAM.

At least gaining something from having to jump through that awkward backward compatibility hoop, the PCI specification demands that upon its first invocation, the shadow RAM location where it now is be _writable_ (!). This is so the expansion "ROM" code can dynamically create tables for their detected devices or whatever, and also allows the "ROM"'s init procedure to ditch code that's no longer needed after init (like SCSI configuration menus and such) and shrink themselves to save space at runtime. Only after POST is the shadow RAM then set to write protected, to again look like a traditional ROM at runtime.

In consequence, the code found on a PCI or AGP card's ROM _expects_ to be run in RAM, and would crash miserably if it weren't.

Can we settle that now? This is growing into a full blown theory lecture ...

regards, Peter

 

[SgtZulu]

please stop it Peter

you're making my head explode

 

[teqwiz]

Just tell him he's right. He likes that.

 

[KF]

>Can we settle that now? This is growing into a full blown theory lecture ...
Thanks for the full blown theory lecture.