VIA and SiS to Launch ClawHammer Chipsets Next Month.

[AGodspeed]

DigiTimes

Here's a little snippet:

Although new processors from Advanced Micro Devices (AMD) based on the 8th generation (K8) core will not hit the market until the fourth quarter, Taiwanese chipset designers VIA Technologies and Silicon Integrated Systems (SiS) already have several products ready. Related motherboards will be showcased at the Computex Taipei exhibition in early June.

As the latest K8-core processor incorporates the memory controller, which is usually set on the north bridge chip, other specifications on the north and south bridge chips have become the focus of competition among the chipset companies.

At present, motherboards based on chipsets from AMD, VIA and SiS have all finished the product design process, board makers said. Product shipments will be able to start as soon as the K8-core processors hit the market. Previously, several companies had planned to put on live demonstrations at Computex. However, to not greatly affect AMD?s K8 processor promotional campaign, Taiwanese board manufacturers will only display their products at the trade show. The live demonstration will be introduced by AMD itself, using the K8 processor and the company?s AMD-8000 chipset.

Given that both motherboard makers and chipset designers have related products ready, when K8-based PCs show up in the market depends only on AMD?s production schedule. [Table Below, see link].

Good lord, I didn't realize the Taiwanese chipset makers were that far into Hammer chipset R&D. Now we'll have to wait and see what ALi and NVidia come up with.

 

[Adul]

holly crap. I guess we shall see hammer in some quantity this oct! w00t

 

[psy44]

Good lord, I didn't realize the Taiwanese chipset makers were that far into Hammer chipset R&D. Now we'll have to wait and see what ALi and NVidia come up with.

Does this mean that if I get a CLawhammer that I will have to get a new video card?

 

[AGodspeed]

Originally posted by: psy44

Good lord, I didn't realize the Taiwanese chipset makers were that far into Hammer chipset R&D. Now we'll have to wait and see what ALi and NVidia come up with.

Does this mean that if I get a CLawhammer that I will have to get a new video card?

Your flexibility to insert a stand-alone video card, to my knowledge, will not be any different with ClawHammer motherboards compared to today's conventional Pentium 4 or Athlon motherboards.

ClawHammer boards will have an AGP slot supporting up to 8x data rates to my knowledge, so there shouldn't be an issue.

 

[BD231]

Good lord, I didn't realize the Taiwanese chipset makers were that far into Hammer chipset R&D. Now we'll have to wait and see what ALi and NVidia come up with.

Wouldn't all the chipset's be practicly identical? I mean if you consider the fact that AMD already took care of the mem controller, and the fact that everyone is rushing to get their boards out (wich leaves no time for optimization), they all are probably using a refrence design right? Just a thought. Also, will we see dual channel DDR with the Clawhammer anytime soon, or am I completely off track? I'm still in the blue as to what memory will be the standard for the Clawhammer.

 

[Booster]

Wouldn't all the chipset's be practicly identical?

No. I wonder what VIA issues people will encounter this time. Incompatibility, data corruption, etc. I can think of a Hammer system paired only with a SiS chipset board.

 

[ST4RCUTTER]

bdog231, I'll try to answer some of your questions.

I think that the fact that the memory controller is integrated will actually force motherboard makers to be more diverse than with more traditional chipsets. Afterall, they will be competing on features, not memory performance. I think we can look forward to boards sporting ATA133, USB 2.0 and firewire, DDR333 in single and possibly dual(please god, Nvidia make a dual-channel Hammer chipset for Opteron!) Overclocking goodness etc. will also be major selling points.

As far as dual-channel DDR for Clawhammer, no we won't. The CPU will only support a single channel of DDR. The specification is for two DDR slots supporting up to 2GB of PC2700DDR. I don't think we'll ever see RDRAM on an AMD chip. DDRII will supplant DDR I for the highend well before RDRAM becomes attractive in the mainstream.

 

[Athlon4all]

Originally posted by: ST4RCUTTER
bdog231, I'll try to answer some of your questions.

I think that the fact that the memory controller is integrated will actually force motherboard makers to be more diverse than with more traditional chipsets. Afterall, they will be competing on features, not memory performance. I think we can look forward to boards sporting ATA133, USB 2.0 and firewire, DDR333 in single and possibly dual(please god, Nvidia make a dual-channel Hammer chipset for Opteron!) Overclocking goodness etc. will also be major selling points.

As far as dual-channel DDR for Clawhammer, no we won't. The CPU will only support a single channel of DDR. The specification is for two DDR slots supporting up to 2GB of PC2700DDR. I don't think we'll ever see RDRAM on an AMD chip. DDRII will supplant DDR I for the highend well before RDRAM becomes attractive in the mainstream.

Well put ST4R. That really is the truth, not just for mobo makers but for chipset makers as well. Performance will be much closer betqween the individiual chipsets.

Man, this is pretty exciting!!!!! This explains all the board makers showing off Mobo's for CH at Computex.!!! I can't wait for CH!!!!

 

[Booster]

The specification is for two DDR slots supporting up to 2GB of PC2700DDR.

Looks like the ClawHammer will be severely memory-bandwidth limited. Single-channel DDR isn't able to deliver maximum P4 performance, and it will for sure cripple ClawHammer's performance too. How sad 🙁. And only 2GB of RAM... Yes, it may seem a lot for now, but in the long run where the Hammer is supposed to win it's just too little, IMO. 🙁

 

[Swanny]

Oh, I do love the Hammer!!

 

[AGodspeed]

Originally posted by: Booster

The specification is for two DDR slots supporting up to 2GB of PC2700DDR.

Looks like the ClawHammer will be severely memory-bandwidth limited. Single-channel DDR isn't able to deliver maximum P4 performance, and it will for sure cripple ClawHammer's performance too. How sad 🙁. And only 2GB of RAM... Yes, it may seem a lot for now, but in the long run where the Hammer is supposed to win it's just too little, IMO. 🙁

Booster, this isn't a conventional processor we're talking about here. The rules have changed now that the memory controller is on-die. Remember, there's no such thing as a FSB (Front Side Bus) now that the NorthBridge's memory controller has been integrated into the processor. Available memory bandwidth rules have changed for Hammer.

 

[ST4RCUTTER]

Looks like the ClawHammer will be severely memory-bandwidth limited. Single-channel DDR isn't able to deliver maximum P4 performance, and it will for sure cripple ClawHammer's performance too. How sad . And only 2GB of RAM... Yes, it may seem a lot for now, but in the long run where the Hammer is supposed to win it's just too little, IMO.


I think you're ignoring certain facts about the Hammer's memory architecture that make current memory designs a poor comparison. First off, the integrated memory controller should reduce memory latencies by quite a large factor. On top of that, as the CPU increases in speed, so does the speed of its memory controller. This is not the case with current motherboards. With Hammer systems, upgrading the processor effectively upgrades the memory subsytem as well. The Hammer will also be running with a much greater effective FSB. The HT links will transfer data at a rate comparative to an 800Mhz FSB. This is a huge jump over the current 266FSB and should provide the bandwidth required for the near future.

edit: Doh! AGodspeed beat me to it...

 

[Bluga]

wow that was fast.

 

[socketman]

Booster, spread your FUD elsewhere. AMD chipsets have never needed the memory bandwidth that the P4s require. Its not limited in the least. Ive seen many Intel BS spreaders point to the low memory bandwidth of AMD systems, but they simply are not as bandwidth hungry as the P4.
WHy put it there if you dont need it. Also, there are only 2 or 3 desktop applications in existence that can saturate the bus anyway. So unless your doing heavy video editing or advanced CAD its a non-issue anyway.

BTW - great news about the chipset makers being ready. I agree they will now have to compete on features..which means the southbridge will be the key. VIA has always had crap southbridges. So im going with SIS. I wish to GOD someone would make an AMD reference south bridge. Unless you get an engineering sample, I dont know anyone who has ever used it.

 

[Lord Evermore]

socketman: I think his point was more that the Hammer core is more likely to need greater memory bandwidth compared to the Athlon in the same way that the P4 needs the bandwidth much more than a P3. If Hammer has a tremendously high clock speed, combined with a high speed bus connecting it to the chipset, then there will be that much greater a need for memory bandwidth. Having a high bandwidth, high speed, low latency connection to the memory controller won't mean jack if the memory it's connecting to is still limited to current bandwidth levels. This is exactly what the P4 runs into when using SDRAM or even DDR compared to RDRAM (I'm not an RDRAM fan, I just acknowledge that it has higher bandwidth, regardless of whether that means significantly higher performance).

 

[Sohcan]

Reducing main memory latency by integrating the memory controller doesn't necessarily reduce bandwidth requirements; the the last level of cache still has an average miss rate resulting in cache line fills. If anything, reducing main memory latency increases IPC and thus main memory bandwidth requirements. Also keep in mind that for a single-processor Hammer system, the HT links are used exclusively for IO and not memory access (ignoring DMA requests from other devices), so you're still limited by the 2.7 GB/sec of memory bandwidth that the initial Clawhammer will provide. Though as ST4RCUTTER pointed out, each new Hammer incarnation can easily bring new memory technology support (it would be stupid not to do so), so the Hammer architecture is by no means "doomed to failure" with its initial PC333 support.

On top of that, as the CPU increases in speed, so does the speed of its memory controller. This is not the case with current motherboards.

This effect was exaggerated a bit by AMD's PR...the DRAM pipe is 19 stages long (not including DRAM access), so at 2GHz the stages have a latency of 9.5ns. Assuming that the load-use latency to DRAM is around 70ns, you can see that little of the latency is occupied by memory controller arbitration. By even doubling the clock rate to 4GHz the speedup is around 7% (1 / (60.5 / 70 + .5 * 9.5 / 70)), yielding a load-use latency of "only" about 65ns. Unfortunately marketing departments rarely understand Amdahl's Law. 🙂

 

[ST4RCUTTER]

Also keep in mind that for a single-processor Hammer system, the HT links are used exclusively for IO and not memory access (ignoring DMA requests from other devices), so you're still limited by the 2.7 GB/sec of memory bandwidth that the initial Clawhammer will provide.

That's spot on. The HT links are for I/O and not memory accesses. I guess what I meant to get across was that freeing up I/O requests from the same bus that is used for memory requests will increase the effective memory bandwidth to the processor. If you look at the chipset topologies of the current leading chipsets (KT266A/KT333) when compared with the upcoming Hammer chipsets this facet becomes more clear. What's especially interesting is that adding CPU's (as in a 4-way SH platform) adds to overall system bandwidth rather than having the opposite effect, thanks to the bus not being shared.

 

[Sohcan]

freeing up I/O requests from the same bus that is used for memory requests will increase the effective memory bandwidth to the processor

It will certainly clear up some IO traffic (strictly speaking in the uniprocessor environment), but it's not that significant. A lot of the high-bandwidth IO traffic is still going to be DMA requests (hard drive read/writes, AGP texturing), and thus consume memory bandwidth. The largest contributor to IO traffic of which I can think that will be relegated strictly to the HT links is non-DMA AGP IO, such as vertex data....though I'm not too keen on the current state of 3D graphics to know how much bandwidth this occupies in today's games.

What's especially interesting is that adding CPU's (as in a 4-way SH platform) adds to overall system bandwidth rather than having the opposite effect, thanks to the bus not being shared.

It's certainly interesting and new in the 2- to 8-way MP environment, but by no means a novel idea altogether. The same NUMA topologies can be applied to MPUs with shared local buses; each node might have 2 to 8 MPUs on the shared local bus with shared main memory, connected to a routing link that interfaces with the other nodes in the topology. Hammer (and the EV7 and Power4) merely integrate these routing links on the CPU and "contain" one CPU per node (in the case of the EV7 and Hammer). The nice thing is that the routing links are already provided in these MPUs, and offer lower communication latency.

This organization is what you often find in 8- to 64-way shared memory address space MP machines. More recently, the HP PA-8700 and McKinley both have the same shared 6.4GB/sec local bus, yet the routing topology of the up-to 64-way Superdome servers allow an aggregate system bandwidth of (IIRC) 64GB/sec.