VHDL syntax question?

[Lord Banshee]

Ok anyone that know VHDL really good can you answer me this?

I am making a hazard controller for a pipeline MIPS32 CPU and the control logic is going to be huge and i wanted to make some shortcuts.

I wanted to do something like #defines in C for example i would like to turn this vhdl

if EXMEM(31 downto 26) = rtype and IDEX(31 downto 26) = rtype then
if EXMEM(15 downto 11) = IDEX(25 downto 21) then control(1)<='1'; end if;
if EXMEM(15 downto 11) = IDEX(20 downto 16) then control(2)<='1'; end if;
end if;

into this

if EXMEM(opcode) = rtype and IDEX(opcode) = rtype then
if EXMEM(rd) = IDEX(rs) then control(1)<='1'; end if;
if EXMEM(rd) = IDEX(rt) then control(2)<='1'; end if;
end if;

is it possible to so such a thing in VHDL? i know it isn't much but this will make the code much easier to read and less typing... i have 29 instructions and about 8x8x3 conditions to meet so i am looking at ~600 lines of code just set the control bits.

thanks in advance,
Chris

 

[esun]

Hmm, I only know Verilog, but in Verilog we have things called "parameters" that are kind of like #defines. For example:

parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b02, S3 = 2'b03;

always @ (posedge Clock) begin
case (State)
S0: State <= S1;
S1: State <= S2;
S2: State <= S3;
S3: State <= S0;
endcase
end

That's one very common usage of parameters (making a state machine basically). Hopefully there are some analogues in VHDL so this makes some sense to you.

 

[Lord Banshee]

those are constants what i want to do that is analogues to your code is something like replaces the 2' with vector2.

I am not even sure if something like this even possible as a #define in C.

I would search google more than i have already but i am not even sure what to call such a thing.

Thanks anyway esun

 

[esun]

Oh, duh, now I get it. You can do that in Verilog, but again I'm not sure how to do it in VHDL. It'd be something like this:

wire [5:0] OpCode;
wire [4:0] rd, rs, rt;

assign OpCode = EXMEM[31:26];
assign rd = EXMEM[15:11];
assign rs = EXMEM[25:21];
assign rt = EXMEM[25:21];

Basically you instantiate a wire that holds the specific bits of EXMEM you want.

 

[Lord Banshee]

esun thanks i think i have seen something like this, I'll post if i figure it out..

Thanks again

*edit* this isn't exactly what i wanted but i can make it work and possible with even less lines writing.

*edit again*

works pretty good
VHDL version
alias rtMEMWB is MEMWB(20 downto 16);

so code is a little shorter and somewhat easier to read lol

if (OpcodeEXMEM = rtype and OpcodeIDEX = rtype) then
if (rdEXMEM = rsIDEX) then control(1)<='1'; end if;
if (rdEXMEM = rtIDEX) then control(2)<='1'; end if;
if (EXMEM = zero) then control(2 downto 1) <= "00"; end if;
end if;