VHDL Simulation Software??

[JC0133]

Not sure if this should be in programming or general software but...

I am in a Logic Design class where we are writing VHDL code for our logic circuits. I want to know if anybody knows the different types of simulation software that is out there?
And if there are free versions I can download to work on my VHDL code at home? Or maybe I can buy the software myself if it isn't to expensive.

 

[Cogman]

For verilog (fairly similar to VHDL) there is http://iverilog.icarus.com/

For both, you can get this
http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm

(xilinks software generally sucks IMO.. but it is fairly standard and free).

I don't know of better options, but these should send you in the right direction.

 

[Modelworks]

The ones I can think of right away are multisim and proteus. Both have trials I think. They are pretty expensive to purchase.
http://www.labcenter.com/index.cfm
http://zone.ni.com/devzone/cda/tut/p/id/5653

 

[chakraps]

For VHDL - http://ghdl.free.fr/

For Verilog

For verilog (fairly similar to VHDL) there is http://iverilog.icarus.com/

This.

And http://www.veripool.org/wiki/verilator

Free EDA Tools: http://opencores.org/opencores,tools