VHDL Latching problems

[polarmystery]

Hey guys,

First off, I'm very new to VHDL. I have a lab assignment that requires some shifting of characters per clock tick (a one hertz pulse). This is the code I came up with, but every time I synthesize I get warnings saying the signals are latching. After I try to program the FPGA, this is apparent and the code doesn't function correctly. I'm not sure how to fix it. Any help/clues?

    shift_char: process(one_Hz_pulse, BTN0, SLIDERSWITCHES, char_temp, chars)
    begin
        if (one_Hz_pulse = '1') then
            if (BTN0 = '1') then
                char_temp <= (others => '0');
            else
                char_temp <= SLIDERSWITCHES;
                chars(15 downto 12) <= char_temp;
                chars (11 downto 0) <= chars(15 downto 4);
            end if;
        end if;
    end process;

 

[esun]

For registered (i.e., edge-driven) sequential logic, typically the sensitivity list will only include the clock and the reset (assuming you're using an asynchronous reset). Remember, the process is re-evaluated whenever any item in the sensitivity list changes. For a sequential process that typically means you only want updates when you have a rising clock edge (or an asynchronous reset).

It's also a good idea to use the rising_edge function when dealing with sequential logic. Here's some typical boilerplate that is used for a process:

my_process: process(clock, reset)
begin
  if reset = '1' then
    -- Reset your output signals
  elsif rising_edge(clock) then
    -- Do whatever you need to do at the rising edge of the clock
  end if;
end process;

 

[polarmystery]

For registered (i.e., edge-driven) sequential logic, typically the sensitivity list will only include the clock and the reset (assuming you're using an asynchronous reset). Remember, the process is re-evaluated whenever any item in the sensitivity list changes. For a sequential process that typically means you only want updates when you have a rising clock edge (or an asynchronous reset).

It's also a good idea to use the rising_edge function when dealing with sequential logic. Here's some typical boilerplate that is used for a process:

my_process: process(clock, reset)
begin
  if reset = '1' then
    -- Reset your output signals
  elsif [B]rising_edge(clock[/B]) then
    -- Do whatever you need to do at the rising edge of the clock
  end if;
end process;

My problem was in bold, I had the enable signal instead of the actual clock. Fixing this seems to have made the problem go away. Thank you for your help!