VHDL Block Rom

[jmcoreymv]

If I infer a block rom in VHDL (to run on a Spartan 2/3), how can I load data into it?

I know if I was using distributed ram then they can be initialized during programming, but how about the block ram?

 

[blahblah99]

You can load initial data into it using a vector file, or by using a clock. It's flexible to the point that you can set it up to clock data in on rising or falling edge of the clock.

 

[jmcoreymv]

Do you have any examples of how this can be done?

 

[blahblah99]

Originally posted by: jmcoreymv
Do you have any examples of how this can be done?

Not at the moment, but... you specify the vector file when you are creating the logicore block ram,

or load data into the ram dynamically during runtime. It's really not that hard to load data during runtime. You set the data, address, and on the rising/falling edge of the clock it latches data. Look at the spec sheet to see what they say about data transfers.

 

[jmcoreymv]

There is no prom chip on the board, I can only program it via JTAG and I have to reprogram it everytime the board is cycled. I haven't been able to figure it out.

 

[blahblah99]

Originally posted by: jmcoreymv
There is no prom chip on the board, I can only program it via JTAG and I have to reprogram it everytime the board is cycled. I haven't been able to figure it out.

How are you generating the block ram? How does the compiler know how big the block ram is? How does the compiler know how wide the block ram is? See where I'm getting at? You have to generate it using Logicore, and in one of those configuration screens you can specify a file, which contains vectors that loadinitial data in each address of the ram.

If you're using the block ram as dynamic ram during runtime, ie - a FIFO, then you'll have to design the vhdl module that interfaces to it.

Good luck.

 

[jmcoreymv]

I am not using the IP Core to generate the block ram. I am using inferred code and the synthesizer figures out to use block ram.

 

[beer]

I did this exact thing a few weeks ago. I inferred distributed ROM, rather than block ROM, but the initialization is the same.
I've sent you a link via PM
Good luck

 

[beer]

On another note, why are you using Block ROM? Why do you want to limit yourself to sync reading? The end result means another stage in the pipeline, relative to async reads.

 

[jmcoreymv]

Im using block rom because I am trying to design a microprocessor in vhdl and in order to increase the instruction memory capacity to a decent size I need to use the block rom. Speed isnt a concern since the processor is going to be used as a learning tool in an academic setting.