VHDL behavior of a gate with a propagation delay and interconnect delay

[duragezic]

I have to write a VHDL listing for this circuit, but I can not find the answer to this question after searching on Google for about 45 minutes.

Everything I've read only talks about and shows examples for transport delays or inertial delays. It doesn't seem like you can use both, but I need to do that.

For example, say I have a OR gate with a propagation delay of 10ps, with the interconnect for input A with a delay of 5ps, and the interconnect for input B with zero delay, and the interconnect for output F with a delay of 10ps.

I don't know how to use both types of delays.

i.e.
...
architecture logic of OR2 is
begin
F <= A or B after 10ps
end

That only considers the propagation delay of the OR gate itself. I don't know how to use 'transport' to have the input have an interconnect delay, then a gate propagation delay before the output F is actually assigned.

Moreover, what if this example OR gate is a gate in the middle of the circuit. If the interconnect that output F is on has a delay of 10ps, do I not worry about that until it becomes an input to the following gate in the circuit?

So in a logic circuit with a few gates with varying propagation delays, as well as some of the interconnects having various propagation delays, when or where do I add a interconnect delay?

 

[Markbnj]

You might have better luck with this one in Highly Technical.

 

[sciencewhiz]

I haven't done much VHDL, but it seems like this should work

architecture logic of OR2 is
signal Adelay, Bdelay : <Whatever>
begin
Adelay <= A after 5ps
Bdelay <= B after 0ps
F <= Adelay or Bdelay after 10ps
end

 

[duragezic]

Yeah that seems like it would work. I thought it would be something simple like that, as our involvement with VHDL is quite limited and deals only with the listing, so I didn't expect to have to use some weird stuff that we were never taught. Just for some reason I didn't think of that.

Or I could probably just nest it like:

F <= (transport(A) after 5 ps) or (transport(B) after 0ps) after 10ps


That might work?

I don't have to compile or test this stuff... I just have to get it right without.