verilog HDL questions

CTho9305

Elite Member
Jul 26, 2000
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1
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What is wrong with creating an rs latch like this:



<< module latch (q,nq,r,s);
output q,nq;
input r,s;

xor (q,r,nq);
xor (np,s,q);

endmodule
>>



as opposed to using some if()'s?