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verilog HDL questions

C

CTho9305

Elite Member
What is wrong with creating an rs latch like this:



<< module latch (q,nq,r,s);
output q,nq;
input r,s;

xor (q,r,nq);
xor (np,s,q);

endmodule >>



as opposed to using some if()'s?
 
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