vega clock domains ?

[Soulkeeper]

So looking at my Vega Fe and going over the powerplay table the defaults can be seen below:

sclk:
p0 852
p1 991
p2 1138
p3 1269
p4 1348
p5 1440
p6 1528
p7 1600

mclk:
p0 167
p1 500
p2 800
p3 945

SoC clock:
p0 600
p1 720
p2 847
p3 960
p4 1028
p5 1107

Disp clock:
p0 282
p1 515
p2 686
p3 800
p4 900
p5 1029
p6 1108
p7 1200


Has anyone done research into the voltages and state transition behavior for these different clock domains ?

I think many of you already know that there is NO memory voltage for vega, it just decides to transition the mclk if the core voltage is above the needed threshold, thus using the current core voltage.
The behavior for SoC and Disp should be similar, but having such a large number of clock states makes it difficult to know what is going on here.

The Disp clock being tied to the sclk, since they both have 7 states, would seem to make sense.
Having 2 fewer SoC states makes that difficult to figure out.
What do you all think ?

I'd love to get some thoughts from anyone else that has pondered this.

 

[CuriousShawn]

AFAIK, some of the SoC clock states are mapped to the memory clock states. For example, you will find that the SoC clock remains below 1107MHz when you set the memory state 0-2 as the maximum state by using WattMan.

And if you change the max core state to p4, the max memory clock will be 800MHz, and the max SoC clock will be 960MHz, so I believe that some of the core/SoC/memory clock states are tied together.

But there may be other variables those affect the SoC clock, as the other components like media engine are in the SoC domain.

 

[Soulkeeper]

AFAIK, some of the SoC clock states are mapped to the memory clock states. For example, you will find that the SoC clock remains below 1107MHz when you set the memory state 0-2 as the maximum state by using WattMan.

And if you change the max core state to p4, the max memory clock will be 800MHz, and the max SoC clock will be 960MHz, so I believe that some of the core/SoC/memory clock states are tied together.

But there may be other variables those affect the SoC clock, as the other components like media engine are in the SoC domain.

Thanks, I can't get a mem voltage reading in linux. What are you getting for mem voltage when the mem is at P1 and P2 ?

 

[CuriousShawn]

Thanks, I can't get a mem voltage reading in linux. What are you getting for mem voltage when the mem is at P1 and P2 ?

HBM2 voltage(MVDDC) is fixed all the time, regardless of its clock.
Actually, the core voltage(=VDDC) changes when you change the memory clock while the GPU itself is idle. I'll put specific numbers from my vega56 reference card below:

When GPU is idle and memory state is at..
P0 - 167MHz mem, 600MHz SoC, 0.750V core voltage
P1 - 500MHz mem, 600MHz SoC, 0.750V core voltage
P2 - 700MHz mem, 719MHz SoC, 0.831V core voltage

The numbers above make me belive that the SoC and Core domains share same voltage, while they are separate frequency domains.