This is true.
And it comes down to the probability of a defect causing yield loss or not causing yield loss, which comes down to the size of the defect and how much "free space" is available within the IC for random defects to exist without critically disturbing the circuits.
Have a less dense layout, less dense xtors and less dense wire routing, and your IC has more places for defects to exist which won't result in the chip becoming non-functional.
In fab parlance, you are always worried about your D0 (defect density) and D0 is particle size dependent as well.
The maximum size a defect can be before causing functional yield loss will be node-specific as it depends on the minimum poly (or fin) pitch and minimum metal pitch.
Being less aggressive on the pitches (less dense layout) will result in higher yields when you have a high D0. As your node matures and the D0 becomes less and less, the yield hit from the D0 will reduce and as such the benefits to having a less dense layout will also be reduced.
However, the reason I suspect you all are at odds here in this conversation is because it appears to me that neither party are speaking to the same issue.
The flip-side of the discussion, using tviceman's quotes example, is that you could have "100mm^2 die that has 1 billion transistors, and a
50mm^2 die that has 500 million transistors" (note the same xtor density now) which would result in approximately twice the number of
chips per wafer.
100mm^2 = 640 chips per 300mm wafer
50mm^2 = 1319 chips per 300mm wafer (never perfectly 2x)
In this case, since both of these theoretical dies would have the same density the D0 impact is such that not only will the smaller die have higher functional yield (percentage-wise), but the total number of chips per wafer (NUBs or net units built) will be all the higher than that of the larger die.
Thus, in practice the only time you would intentionally layout your chip to have low density
for the sake of functional yield is if you are expecting (because you start this process 2-3 yrs before taking the chip to production) the D0 for your production node and fab to be absurdly high.
But there are other reasons,
for the sake of parametric yield, for which you would intentionally go about designing less dense circuits and ICs. Sram for L1/L2/L3$'s is but one very easy to identify example of this. Operating voltage is yet another, as well as heat dissipation and power consumption (leakage), etc.