Triple Channel AM3 Chip in the future?

[legocitytruck]

It is possible or are there any known future plans of AMD's to roll out a AM3 socket based chip that supports triple channel DDR3?

 

[Idontcare]

Nothing even in the remotest of speculations and rumors has triple-channel been whispered for AMD and AM3. Next up for them is quad-channel when BD comes out.

Other than the synthetic benchmarks, there really isn't anything in the consumer desktop world that benefits (maybe winrar) from the bandwidth that comes with that third-channel on the x58 platform anyways.

 

[Fox5]

I don't think triple channel is really needed given how fast DDR3 is in relation to what can actually be used right now. Dual channel DDR3 1600 already does 25.6GB/s, which would saturate the hypertransport bus.

 

[legocitytruck]

Originally posted by: Idontcare
Nothing even in the remotest of speculations and rumors has triple-channel been whispered for AMD and AM3. Next up for them is quad-channel when BD comes out.

Other than the synthetic benchmarks, there really isn't anything in the consumer desktop world that benefits (maybe winrar) from the bandwidth that comes with that third-channel on the x58 platform anyways.

What is BD?

 

[cusideabelincoln]

BD = Bulldozer, I'm assuming.

 

[BitByBit]

The extra bandwidth afforded by triple channel DDR3 only really makes sense on i7 platforms, and even then only in select applications that can make use of all 8 threads. Maybe AMD's decision to incorporate a Quad Channel memory controller with Bulldozer is an indication of potential performance?

Dual channel DDR3 1600 already does 25.6GB/s, which would saturate the hypertransport bus.

The Hypertransport and memory buses are totally independent.

 

[Idontcare]

Originally posted by: cusideabelincoln
BD = Bulldozer, I'm assuming.

Yep.

 

[drizek]

Ya, I don't see triple channel happening. Remember, AMD waited a year to switch to DDR3 because they felt it didn't offer a major performance benefit for hte money. That was a good call, and I think not going for triple channel is a good call as well, the difference is really not noticeable at all.

 

[Fox5]

Originally posted by: BitByBit
The extra bandwidth afforded by triple channel DDR3 only really makes sense on i7 platforms, and even then only in select applications that can make use of all 8 threads. Maybe AMD's decision to incorporate a Quad Channel memory controller with Bulldozer is an indication of potential performance?

Dual channel DDR3 1600 already does 25.6GB/s, which would saturate the hypertransport bus.

The Hypertransport and memory buses are totally independent.

Oh, so if the memory offered additional bandwidth beyond what the hypertransport bus could handle, the processor could make use of it? The max bandwidth of HT3.1 on AMD's processors is 25.6GB/s, the same as the max speed DDR3 supported.
The QPI bus on current i7s 19.2GB/s, but support up to 25.6GB/s. If you count the data bits used for error correction and header information, then the i7 does 32GB/s.

Coincidentally, this is approximately the bandwidth reported in memory bandwidth tests with triple channel memory, whereas triple channel DDR3-1600 should be capable of 38.4GB/s. That's with the QPI bus at the higher speed, or even slightly overclocked. At stock speeds, benchmarks report around the 19.2GB/s number of lower.

My supposition is that the processor can't use more memory bandwidth than QPI or HT provide, but tell me if I've got that wrong.

 

[BitByBit]

RAM on AMD systems is not accessed over Hypertransport.
See diagram: Link
Hypertransport connects the processor to peripherals and other processors on MP platforms.

 

[IntelUser2000]

Originally posted by: Fox5

Oh, so if the memory offered additional bandwidth beyond what the hypertransport bus could handle, the processor could make use of it? The max bandwidth of HT3.1 on AMD's processors is 25.6GB/s, the same as the max speed DDR3 supported.
The QPI bus on current i7s 19.2GB/s, but support up to 25.6GB/s. If you count the data bits used for error correction and header information, then the i7 does 32GB/s.

Coincidentally, this is approximately the bandwidth reported in memory bandwidth tests with triple channel memory, whereas triple channel DDR3-1600 should be capable of 38.4GB/s. That's with the QPI bus at the higher speed, or even slightly overclocked. At stock speeds, benchmarks report around the 19.2GB/s number of lower.

My supposition is that the processor can't use more memory bandwidth than QPI or HT provide, but tell me if I've got that wrong.

The QPI on Core i7 965EE is 6.4GT/s which equals to 25.6GB/s. All other Bloomfields are 4.8GT/s. Couple of faster Gainstown are also 6.4GT/s.

The reason it doesn't show theoretical bandwidth is no memory controllers are 100% efficient. Add to that, going to multiple channel loses a little bit of efficiency.

Maybe AMD's decision to incorporate a Quad Channel memory controller with Bulldozer is an indication of potential performance?

That could be what will happen with server processors of BD.

 

[hans007]

Originally posted by: BitByBit
RAM on AMD systems is not accessed over Hypertransport.
See diagram: Link
Hypertransport connects the processor to peripherals and other processors on MP platforms.

yeah, in theory you could take advantage of ram faster than the hypertransport bus.

say you had a giant data set you could fit entirely in memory. you could work on it without hitting hypertransport ,as all hypertransport does is connect the chip to the i/o bus etc.

granted if you ever had to use i/o it would bottle neck, but thena gain if you have 7-8 cores and only one is waiting on I/o the other 7 would be fine taking advantage of memory (and if you had to say write to disk, you could have only one cpu block on i/o)


that said, it probably would be in a really rare case so its probalby not worth it for amd to do it. if you had a dual socket machine using numa, then memory is limited by hypertransport if you are accessing memory connected to another cpu. at least thats my understanding of how this should work.

in the future once they have cpus with say fusion, faster memory than hypertransport will be important for the integrated graphics as well. (on intel 775 chipsets, you can take advantage of memory that has more bandwidth than the gtl+ bus, in this way... say dual channel ddr2-533 on a cpu with fsb 800mhz)

 

[BTRY B 529th FA BN]

Originally posted by: Idontcare

Originally posted by: cusideabelincoln
BD = Bulldozer, I'm assuming.

Yep.

aint seen you in a while

 

[ilkhan]

As they said, with the on die memory controller, memory access doesn't touch the HT (or QPI) bus like it did with the old FSB. Totally independent. QPI/HT connect to either the northbridge or additional sockets.