Transistor depth ?

[pm]

Citation?... I mean I would assume that's correct, even the 80386 was designed with the connections underneath.

I tried searching for cross sections, but other than schematics and close-ups of a single transistor... was surprised not to find "I broke my Sandy Bridge in half, and this is what it looks like" sort of images.

The 386 was not designed with the connections underneath. I searched through Google for a while, but I never found a good image of the way that the 386 was wired, but way back when, chips used to look like this:
http://www.extremetech.com/wp-content/uploads/2011/11/pentium-pro.jpg

You can see the silicon in the middle and it's front-side up (substrate "bottom" down) and then gold wires from the package attached to the sides of the silicon on the sides.

Flip-chip packaging techniques in x86 processors showed up around the year 2000 and ever since then, the chips are flipped upside-down and then soldered to the package using a ball-grid array so that when you see a die in a package, you are seeing the bottom/backside of it.

 

[Vectronic]

The connections are still on the under-side though

_[]_ not ¯[]¯ as was the case with older chips where the silicon sat in a "pool" like shown there, and the connection nodes rained down from the sides like a fountain.

What I meant is that, the subtrate/dead silicon has been on the top-side for quite awhile, not specifically flip-chip.

 

[Charles Kozierok]

What I meant is that, the subtrate/dead silicon has been on the top-side for quite awhile, not specifically flip-chip.

Pretty sure that's not true. The entire point of "flip chip" is that the chip has been "flipped" relative to the package/substrate.


I realized that I had a good PPT in my huge cache of materials saved for my PC Guide rewrite.

This is a Powerpoint presentation that describes wire bonded and flip chip packaging very well, with lots of diagrams. Pay attention to page 4 for an illustration of conventional wire bonding to the top of the chip. Then look at page 13 which shows how FC works.

 

[pm]

Pretty sure that's not true. The entire point of "flip chip" is that the chip has been "flipped" relative to the package/substrate.


I realized that I had a good PPT in my huge cache of materials saved for my PC Guide rewrite.

This is a Powerpoint presentation that describes wire bonded and flip chip packaging very well, with lots of diagrams. Pay attention to page 4 for an illustration of conventional wire bonding to the top of the chip. Then look at page 13 which shows how FC works.

No, I'm actually in agreement with Vectronic now, he's right. The substrate has always been up for CPU's for as long as I can remember. While the BGA connections on page 4 look correct to me, that's for the smaller plastic BGA parts. The larger ceramic ones we used to use had the CPU in the middle, with the subtrate facing up (towards the CPU's heatsink/fan) and then gold wires out on the sides. to pins which were on the outside of the actual IC.

I'd forgotten all of this when I posted my reply to Vectronic on the previous page. What I remembered was that it was a lot easier to probe the older ceramic packaged parts because you could see the wires of the CPU and you could etch the top layers off and directly look at the top metal routing (using an electron beam) and nowadays you have to come in from the backside to do any probing or FIB (focused ion beam) work and I got it in my head that the die used to be the other way... but I was wrong and Vectronic is correct. For CPU's anyway. For smaller die, they look like your slideset's page #4.

 

[Vectronic]

Holy s**t people... are you serious?

Look through the history of Intels PGA/LGA for desktop CPUs and show me one that was made in the last 4 generations lets say, where the substrate wasn't on the top.

"I would assume that's correct"... meaning why would Intel all of a sudden go back to 1990's designs for Ivy Bridge?

I realize there are many ways to design a chip, but I was specifically talking about Intel, and desktop CPUs.

Edit: not allowed to delete, so this stays.

 

[Charles Kozierok]

No, I'm actually in agreement with Vectronic now, he's right.

Sorry, but he's not.

The substrate has always been up for CPU's for as long as I can remember.

That's because Intel went to flip chip packaging in the Pentium III era, and exclusively flip chip starting with the P4. That's more than a decade back. But the older chips were indeed mounted with the die facing up (relative to the package substrate).

While the BGA connections on page 4 look correct to me, that's for the smaller plastic BGA parts.

Flip chip refers to the connection of the die to the package. It can be (and is) used with BGA, PGA and LGA.

Flip Chip Overview -- “Flip chip” is an industry term used to describe the electrical connection of face-down processor die onto the package by means of conductive bumps (the round bumps in the illustration below) on the chip bond pads. Flip chip assembly replaced older wire bonding, which used face-up chips with a wire connection to each pad.

http://www.intel.com/pressroom/kits/45nm/leadfree/lf_backgrounder.pdf

That's pretty much from the horse's mouth. But really, look at any diagram of conventional wire bonding, and you'll see the wires run from the top of the die to the package connections. That means the die is face up. With flip chip, it's face down -- that's what "flip chip" means.

ETA: Here is a large picture of a P5 era Pentium with MMX. You can see the die is "face up" relative to the package. (The whole thing is upside down because they put it under the substrate, but the bottom of the die is against the package, not the top.)

 

[Idontcare]

Sorry, but he's not.



That's because Intel went to flip chip packaging in the Pentium III era, and exclusively flip chip starting with the P4. That's more than a decade back. But the older chips were indeed mounted with the die facing up (relative to the package substrate).



Flip chip refers to the connection of the die to the package. It can be (and is) used with BGA, PGA and LGA.



http://www.intel.com/pressroom/kits/45nm/leadfree/lf_backgrounder.pdf

That's pretty much from the horse's mouth. But really, look at any diagram of conventional wire bonding, and you'll see the wires run from the top of the die to the package connections. That means the die is face up. With flip chip, it's face down -- that's what "flip chip" means.

ETA: Here is a large picture of a P5 era Pentium with MMX. You can see the die is "face up" relative to the package. (The whole thing is upside down because they put it under the substrate, but the bottom of the die is against the package, not the top.)

Everything CharlesKozierok is saying here is exactly how I understand it to be as well.

I suspect folks might be getting confused by the terminology, confusing package substrate with "silicon" substrate (i.e. the silicon) and so forth. Just a guess as to how so much confusion can transpire.

 

[Charles Kozierok]

Thanks IDC.

I think it's mainly two things causing the confusion: first, it's been all FC for over ten years. Ad second, the old style was "not upside down" in terms of die versus package, but the die itself was usually upside down between the pins.

Anyway, if you can see the patterns on the die when it's on the package, it's not flip-chip.

 

[pm]

Everything CharlesKozierok is saying here is exactly how I understand it to be as well.

I suspect folks might be getting confused by the terminology, confusing package substrate with "silicon" substrate (i.e. the silicon) and so forth. Just a guess as to how so much confusion can transpire.

I worked on the chip that that photo came from - I was on P54CS and (briefly) on P55C (the Pentium w/ MMX). I did circuit design, and then debug, and a bit of quality/reliability I can take a photo of my plaque if you want.

So yeah, this must be a terminology difference because we all seem to be saying the same thing in different ways. The silicon substrate was oriented up (metal layers down) in both ceramic and flip-chip, not relative to the package substrate, but relative to the heatsink/motherboard. But then if you are talking relative to the package, then yeah, they are clearly on opposite sides of the package.

 

[Idontcare]

I worked on the chip that that photo came from - I was on P54CS and (briefly) on P55C (the Pentium w/ MMX). I did circuit design, and then debug, and a bit of quality/reliability I can take a photo of my plaque if you want.

So yeah, this must be a terminology difference because we all seem to be saying the same thing in different ways. The silicon substrate was oriented up (metal layers down) in both ceramic and flip-chip, not relative to the package substrate, but relative to the heatsink/motherboard. But then if you are talking relative to the package, then yeah, they are clearly on opposite sides of the package.

Near as I can tell, Charles is fixated on discussing flip-chip. When it is being used and when it isn't. Flip-chip itself is package-agnostic.

Whereas you and Vectronix appear to be fixated on making distinctions regarding IC orientation on a package-basis, which is never going to be universally applicable because of the flip-chip factor that sometimes (but not always) comes into play.

I think you both are right, just not talking about the same thing maybe.

 

[Charles Kozierok]

So yeah, this must be a terminology difference because we all seem to be saying the same thing in different ways. The silicon substrate was oriented up (metal layers down) in both ceramic and flip-chip, not relative to the package substrate, but relative to the heatsink/motherboard. But then if you are talking relative to the package, then yeah, they are clearly on opposite sides of the package.

Okay, gotcha. I think I forgot you were an Intel guy, so sorry for my previous post, which you may have found insulting or silly.

My fixation on flip chip, IDC, is tied to the topic of the thread, which is basically "will a chip work if you scratch or damage the part where the heat sink goes". And the answer is basically "no, because the bottom of the chip faces out". With the old chips, I guess you could destroy the chip by scratching the top of the die, but it was hidden underneath anyway so that wouldn't be likely to happen.

So I guess we've been talking past each other.

 

[Vectronic]

The original question was about how thick the material was on the top of the "important parts" of the CPU, how the chip is mounted or connected doesn't really matter, it could have connections on 5 of the 6 sides.

That's where it all got lost.

Sure the OP didn't specify PC CPUs, but it's safe to make that assumption given the forum.

 

[pm]

Okay, gotcha. I think I forgot you were an Intel guy, so sorry for my previous post, which you may have found insulting or silly.

My fixation on flip chip, IDC, is tied to the topic of the thread, which is basically "will a chip work if you scratch or damage the part where the heat sink goes". And the answer is basically "no, because the bottom of the chip faces out". With the old chips, I guess you could destroy the chip by scratching the top of the die, but it was hidden underneath anyway so that wouldn't be likely to happen.

So I guess we've been talking past each other.

Yeah, I think it's my fault... I'm not sure why I was even discussing which side it was on the old chips. Except that I remember those old packages fondly.

And, no, I didn't find it insulting or silly... more amusing. I saw that photo and thought "I remember sticking pico-probes down on the surface of that thing".

 

[Charles Kozierok]

The original question was about how thick the material was on the top of the "important parts" of the CPU, how the chip is mounted or connected doesn't really matter, it could have connections on 5 of the 6 sides.

Right, well, I brought up flip chip because I was basically trying to say "it doesn't matter how far the transistors go into the substrate for the purposes of worrying about scratching/engraving, because that side of the die is soldered to the package".

 

[Idontcare]

ie: how deep of a scratch can you make on a surface before damage is done.

This is a relevant question though, despite the point we have all belabored in that the active circuits themselves are not exposed at the "surface" we all see on a modern delidded CPU.

The backside of the IC is hermetically sealed from the environment with a thin (relatively speaking) layer of silicon nitride or polyamide.

This thin layer is optically transparent but will give the impression of having a color because of Fabry–Pérot interference, like a peacock's tail.

At any rate, it is at most around 50um thick, usually only around 20um thick. And it keeps out a few things in the environment that are known to degrade the xtors - hyrogen and water being two examples.

If you scratch through this hermetic seal then your chip won't immediately die, but it is compromised and depending on your regional atmospheric conditions (humidity and trace gas concentrations) your CPU would be expected to degrade and stop functioning much sooner that intended.

The second bad thing to come from scratching your chip is that the propensity for cracks to propagate through the chip (cracking it entirely) is strongly dependent on the size of the largest flaw present in the chip.

In fracture mechanics this is referred to as the critical crack length. The rule of thumb is that the force (stress) required to cause a crack to propagate through an object is reduced as the length or size of the crack increases (by the square root of the scratch length before it turns into a propagating crack).

Or in other words, a non-scratched chip will withstand a far greater amount of mechanical force than a scratched chip. So best off not scratching it at all. But if you do, longer (and deeper) scratches are much worse for fracture toughness than shorter (or shallower) scratches.

 

[erunion]

+1 IDC.

Many IVB dies have been killed from being scratched/cracked while removing the IHS. So its definitely a possibility.

 

[Vectronic]

semi-off-topic, but has there been any sort of unofficial or official studies done on Ivy Bridge and when to de-lid? ie: as soon as you open the box vs. 6 months of use.

Does it become easier or harder?
How well does the TIM hold up?
Have any just spontaneously separated from the IHS?

Possibly worthy of it's own thread. /lazy

 

[Charles Kozierok]

+1 IDC.

Many IVB dies have been killed from being scratched/cracked while removing the IHS. So its definitely a possibility.

I'll defer to IDC's answer on this, but I'd imagine any IB chips killed by delidding are either due to cracking the die or stresses causing fracturing of the solder connections between the die and the substrate. Can't imagine simple surface scratches doing one in.

 

[Idontcare]

I'll defer to IDC's answer on this, but I'd imagine any IB chips killed by delidding are either due to cracking the die or stresses causing fracturing of the solder connections between the die and the substrate. Can't imagine simple surface scratches doing one in.

The saying is "every crack begins its life as a scratch".

If you have cracked your die then you are guaranteed at some point in time beforehand you had initially scratched the die...and subsequently (perhaps mere nanonseconds later) you then proceeded to apply enough stress to that scratch as to exceed the then reduced fracture toughness of the material in question; thereby causing the crack tip (the scratch) to propagate through the material inducing catastrophic failure.

If you manage to create a scratch but simultaneously avoid causing the scratch to near-immediately turn into a crack then you have simply delayed the inevitable. At that point time is your enemy, and you can only keep delaying the inevitable by handling the object in question ever more gently over time.

A good analog here is your car's windshield and the creation, and subsequent propagation, of a crack in the windshield once chipped by a rock.

If the rock doesn't cause an immediate crack across the windshield then you know you are merely living on borrowed time until the otherwise normal road-vibration stresses (which wouldn't normally cause a crack in the first place) causes a crack to form and propagate across your windshield.

And you know what windshields and silicon wafers have in common (hint: sand )

 

[Charles Kozierok]

The saying is "every crack begins its life as a scratch".

I get that.. but isn't it more of a degradation-over-time thing? Not an "I delidded my IB CPU and now it's dead" sort of thing? I'd think you'd need to do more than just scratch the back of the die for that to happen.

 

[Abwx]

A fraction of a mm is left inert at each side of the die square so even removing
a little part of the cristaline structure wont kill the CPU in many cases.

What is lethal are uncontrolled shocks concentrated in a very little
area and wich , like with glass , create a microscopic and invisible
cracks of the inner die structure.

Often , the die can work at first but will fail due to thermal
dilatation that act as a hammer for the coup de grace....

 

[Idontcare]

I get that.. but isn't it more of a degradation-over-time thing? Not an "I delidded my IB CPU and now it's dead" sort of thing? I'd think you'd need to do more than just scratch the back of the die for that to happen.

If the scratch remains just that, a surface scratch, then it will be a degradation-over-time thing "at worst".

Odds are with you that the degradation would be so slow that you'd retire the CPU before you observed an in-field failure stemming from the scratch.

If you apply enough compression to the CPU, and cycle it through enough thermal cycles as to cause the scratch to grow into a crack, then your chip could die at any time. Could take just one day, could take 15 yrs.

You would know though if that happened, simple visual inspection of the silicon die would give you indication if a crack had transpired. It would be easily visible with the unaided eye.

But, putting all that aside, IMO it is an entirely different topic to discuss the pareto of failure mechanisms that appear to be afoot when people instantaneously kill their IB chips whilst delidding.

Going on the volume of anecdotal reports, people seem to kill their chips by nicking the CPU PCB too deeply while attempting to pry the IHS off the PCB. I have only seen a few reports on various forums in which a person killed their IB by way of actually chipping the corner of the silicon (and presumably propagating a crack through the active region).

And I have only seen one case reported in which the silicon die itself was sheared off the PCB (severed at the soldered interface).

But that is the problem with canvassing user-submitted failure analysis, not only are you blind to the totality of the failures (tip of the iceberg situation) but you are also limited to the analysis skills of the individuals who are assessing their own dead chip(s).