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Transistor depth ?

Soulkeeper

Soulkeeper

Diamond Member
How deep are the transistors actually buried in modern silicon ?

ie: how deep of a scratch can you make on a surface before damage is done.
Noting that laser etching of logos/numbers are commonly put on dies, i'm just curious.
 
Before you get to the transistor, you're gonna be scratching the metal layers. That could break functionality too.
 
The layers that make the chip functional are extremely thin compared to the thickness of the silicon substrate. But modern chips are essentially mounted upside-down, so the "up" surface is just silicon, and anything done to it will really not affect operation (within reason).
 
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CharlesKozierok said:
... modern chips are essentially mounted upside-down, so the "up" surface is just silicon, and anything done to it will really not affect operation (within reason).
Click to expand...
Citation?... I mean I would assume that's correct, even the 80386 was designed with the connections underneath.

I tried searching for cross sections, but other than schematics and close-ups of a single transistor... was surprised not to find "I broke my Sandy Bridge in half, and this is what it looks like" sort of images.
 
That's what the "flip" is in "flip chip" packaging. 🙂 The transistor and metal layers are built up, and solder bumps put on the top metallic layers for connection to the package. It is then flipped upside down and reflow soldered to the package, then underfilled.

In fact, in some cases they actually "back lap" the water, grinding off some of the substrate to make it thinner.
 
Yeah some kind of cross section image would be nice.

plenty of artist depictions like this:
38626_sourcegated_transistor_diagram_large.jpg


What they label as "Glass" being maybe a few nm thick on a 32nm process maybe ?
 
CharlesKozierok,

Your image is of a chip package, not of the die. Soulkeeper's image is of the die. The part labeled "Die" on your image is actually several layers. Chips do commonly have several metal layers between the heatsink and the silicon. These layers have the "wires" that connect the transistors to each other and channel power and data throughout the chip.

This site has a good image of what a cross section of the layers in a die look like.
 
Yes, it's the chip package, but it shows how the die is flipped upside down with solder joints connecting to the package (in this case, BGA).

I don't think there are any scale images of chips that show both the details of the layers and the thickness of the substrate, because they differ in thickness by many orders of magnitude (nanometers versus on the order of a milimeter).

The article you linked seems to be about 3D chip technology, which is a whole 'nuther ball of wax.
 
I think the starting thickness of 12" wafers is around 3/4 of a mm. That's about 750,000 nm, so you can remove quite a bit of that material off the back without hitting the circuitry.
 
According to this mumbo-jumbo... 775,000nm... and according to this gibberish, it starts off at "about 1mm" before polishing, and if we assume that the little diagram is even approximately accurate, about 1/3rd of that original 775um to 1mm is dead.
 
CharlesKozierok said:
The layers that make the chip functional are extremely thin compared to the thickness of the silicon substrate. But modern chips are essentially mounted upside-down, so the "up" surface is just silicon, and anything done to it will really not affect operation (within reason).
Click to expand...

Good point on this.
 
Soulkeeper said:
that sounds reasonable
essentially orders of magnitude thicker than the transistors

thanks
Click to expand...

The rule of thumb is this - if you were to scale the substrate thickness to be a 10-story building, the active region of the IC would be contained within the the top 6 inches of the building.

If you cleaved a die in half, even one that has been thinned via backgrind, to your eye you'd be holding a peice of glass that was roughly 0.5mm thick and the metal layers + transistors would be thinner than a layer of paint.
 
CharlesKozierok said:
IDC, do you know to what extent back-lapping is done, under what circumstances, and how much?
Click to expand...

It is completely application dependent.

I've seen chips that went into applications where they were thinned to the point they were transparent (you could literally see through them), the wafer itself flopped and sagged under its own weight like a wet paper towel.

rpi_thinned_wafer.jpg



pict_downsizing_07.jpg
 
Wow.

Is that last image really a standard silicon wafer back-lapped? I wouldn't have thought you could get it to curl like that no matter how thin it was.

Of course all of this then leads to the obvious question of why they don't just cut them thinner in the first place. Must be some sort of issue related to handling during manufacture.
 
CharlesKozierok said:
Wow.

Is that last image really a standard silicon wafer back-lapped? I wouldn't have thought you could get it to curl like that no matter how thin it was.

Of course all of this then leads to the obvious question of why they don't just cut them thinner in the first place. Must be some sort of issue related to handling during manufacture.
Click to expand...

Yeah its all standard processing, nothing unusual to be seen in those pics.

Wafer thickness during processing is 100% solely dictated by the mechanical rigidity (structural integrity) requirements for handling of the wafer throughout the fab.
 
Idontcare said:
Yeah its all standard processing, nothing unusual to be seen in those pics.

Wafer thickness during processing is 100% solely dictated by the mechanical rigidity (structural integrity) requirements for handling of the wafer throughout the fab.
Click to expand...

Yep. The machines would snap the wafers if they were super-thin.
 
CharlesKozierok said:
I still can't accept that that last picture is really a lapped standard wafer on solid silicon. Honestly? 🙂
Click to expand...

I don't know if it ever made it onto the internet but I use to have a video file showing someone waving a 300mm wafer like it was a flag after it had been through a specialized wafer thinning process.

Not all wafers are thinned to that degree though, obviously, it all depends on the target application for the IC in question.
 
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