Transistor Density

[witeken]

Dropping the frequency target by over 1 GHz? I have to imagine they will have re-run their physical design flows. I mean, you work at Intel so I differ to you but I can't believe that's how it goes. If so, well I guess I know one reason Core M didn't deliver as expected compared to ARM designs which are always implemented for particular targets. I mean you have an extra 170ps going between 3 and 2 GHz, does process variation eat all of that up in binning? Maybe it does, I guess I don't know 14nm parameters. I am completely aware of the cost in man-hours, but the cost of releasing sub-par products seems awful high - well something to the tune of $4.21 billion I think 😀

According to Intel, 14nm was natively optimized for BDW-Y.

 

[witeken]

You bet you would have to rerun the physical design flow and rebuild an incredible number of custom designs again using whatever new library cells and design rules and frequency/voltage target you want to target. It can be done but it's incredibly expensive and the return is questionable.

Can('t) it be automated?

 

[videogames101]

Can('t) it be automated?

🙂

That's what Synopsys will (s/t)ell you.

The reality is that EDA (electronic design automation) tools require a large (read: very large) amount of manual input and tinkering by engineers to get good results.

Although I hear IC Compiler II offers a 10x throughput increase this year 🙄

 

[TuxDave]

Can('t) it be automated?

All designs can be "more automated" with your typical design sacrifices. And you can allocate less people on synthesis designs (synthesis is not push button work) with even more design sacrifices. Those two are always theoretically available.

 

[Enigmoid]

What is the area of a BDW core.?.

About 10 mm^2 including L3 cache.

Because in general the GPUs have higher density than CPU cores.

There is a ton of dead space on the GT3 die.

Beside the memory controller would be one area.

 

[sm625]

Doesnt the GT3 die also contain the L4 cache controller? Couldnt that explain a loss of density? They probably just slopped it in there and left a lot of dead space because it is a lower volume higher margin part.

 

[krumme]

I think an SoC like 5Y10 wouldn't get hurt a lot with a much higher density, but this is where Atom comes into play, which has a higher density than Core.

Well - if at all - how much? Or is the answer 4B? 🙂