Question Threadripper Pro 5000 announced

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dnavas

Senior member
Feb 25, 2017
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What makes you think ... 56C/112T Sapphire Rapids ... will be competitive with a Zen 3 64C/128T ThreadRipper Pro?
One makes assumptions. I note that the TR Pro doesn't just have a 64 core sku. I'd also note that I'm not likely interested in the high-end, and the 24 core got resurrected, so I'm not alone.... Also, we have no idea about pricing. I would hope HEDT $ < Workstation $, but this is also AMD $ vs Intel $, so....
The Thinkstation P620 isn't cheap if you price out something for 32 cores. Leastwise not in my book, ymmv.

...cooled and kept under TDP.
Yeah, I think I might have mentioned that one. But I think the whole AMD vs Intel thing is boring. I think HEDT is AMD's to lose, and AMD appears to be busy making the moves to ensure that outcome. At least that's the way I see it being sold in the press (TR is dead, long live TR Pro). I'm unconvinced.

In my head, AMD decided to direct a ton of production towards Milan, TR kept getting deferred (I've got a bone to pick about doing that while we were all at home working, but nm for now (*)), and now they're coming up against the Zen4 launch. Zen4 isn't just a core upgrade, it's a whole bunch of connectivity upgrades (memory/pcie), and their competition beat them to it (oops). They have these b-to-b agreements regarding TRPro that they have to live up to, so fine, they're doing that, but otherwise.... Drop the TR-Zen3, there's no point in launching it after TRPro-Zen3, and there's no way their partners are going to wait for a whole TR launch cycle to get to TRPro. Aside from which, AlderLake forced them to ship Zen3-X, which just makes for too many moving pieces. Optimistically, TR could launch 5 months after Zen4 desktop (that's what happened in 2017 iirc), which would bring it in quite close to the SR-AP launch. Pessimistically, Microsoft has bought every platter TSMC can manufacture and no one is seeing anything for awhile. I'm also interested in when 3000Embedded is going to rev (if ever), and when V3000 is going to appear, which has no place in a TRPro thread, except that I think all of the coordination of these launches are intertwined with the decisions on which things are going out when.

Edit (*) okay, I can't help myself. I thought it would be smarter to launch TR before AM5 due to DDR5 and pcie5 premiums. Why not add that premium to the platform with higher margins and defer creating the AM5 IO die (leveraging the work you're already doing for Genoa). And then I saw the Genoa package :]
 
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nicalandia

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Jan 10, 2019
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In my head, AMD decided to direct a ton of production towards Milan, TR kept getting deferred
I can't blame them, 2021 and 2022 have been a very hard Years due to a Pandemic and Chip Shortages so they have to prioritize the precious silicon wafers for the most profitable products. In this Case Milan is Selling like Hot Cakes. Also Intel have neglected their HEDT segment because they just did not have anything else as competitive.
 

jamescox

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Nov 11, 2009
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I thought it was only the earlier Zen and Zen+ threadrippers that used NUMA?
I don’t know what numa options Threadripper have due to only 4 channel memory. I deal with Epyc processors at work though. They have several options due to the distributed L3 cache and the IO die being divided into quadrants. You can set it to treat each L3 cache as a separate numa domain. You can also split it by the IO die quadrants, which effects how the memory is interleaved. NPS1 (Numa per socket) will result in 1 numa node with memory interleaved across all 8 channels. NPS2 will have 2 domains per socket, each with memory interleaved across 4 channels. The NPS4 setting is each quadrant is a separate domain with memory interleaved across 2 channels.

Do Threadripper CPUs have some of these settings or only game mode?
 
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nicalandia

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I don’t know what numa options Threadripper have due to only 4 channel memory. I deal with Epyc processors at work though. They have several options due to the distributed L3 cache and the IO die being divided into quadrants. You can set it to treat each L3 cache as a separate numa domain. You can also split it by the IO die quadrants, which effects how the memory is interleaved. NPS1 (Numa per socket) will result in 1 numa node with memory interleaved across all 8 channels. NPS2 will have 2 domains per socket, each with memory interleaved across 4 channels. The NPS4 setting is each quadrant is a separate domain with memory interleaved across 2 channels.

Do Threadripper CPUs have some of these settings or only game mode?
ThreadRipper PRO have 8 Channel Memory
 

jamescox

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Nov 11, 2009
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ThreadRipper PRO have 8 Channel Memory
Yes, it is a rebranded Epyc. The non-pro Threadripper only has 4 channel. Does the 4 channel still allow you to configure more than 1 numa node? I don’t have any Threadripper processors, only Epyc.
 

dnavas

Senior member
Feb 25, 2017
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Does the 4 channel still allow you to configure more than 1 numa node? I don’t have any Threadripper processors, only Epyc.
I seem to remember playing with that on mine, but I don't have a Zen2 TR, so I can't speak to that.
 

Markfw

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I seem to remember playing with that on mine, but I don't have a Zen2 TR, so I can't speak to that.
I have a 1950x, running linux. Could I help by running something ? I also have a 2970wx running windows.
 
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JoeRambo

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Jun 13, 2013
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1950x is anemic at best. It has 8MB of L3 available maximum for single threaded loads, has ZEN1 core that limited to 4Ghz max clock and ZEN1 weakest point - memory latency is made worse by 4C mem.
So even in AMD parlor it is missing two generations of 20% performance increases. Anything ZEN3 or ADL is 50% faster.

Back in the day they were good for rendering or DC workloads, i'd not touch them for interactive desktop style workloads. Even for rendering, it has ~12700K performance with all single core drawbacks.

Now Z690 and X570 do have some great boards, and the CPUs they support would be great for my use case, but they are still limited by chipset design in terms of IO.
I'd not discount Z690 so quick tho. They can connect 3x drives with full performance. One is connected directly to CPU via 4xPCIE4, and two more to chipset via 4xPCIE4 that is no longer bottlenecked by 4xDMI3 from Skylake era, now they have moved to 8xDMI4 -> basically 8xwidth PCIE4.
And there is also nuclear option of using PCIE5 16x slot for bifurcating into 4xPCIE4, i think i've seen some options in BIOS for bifurcation, maybe someone has tried it already.

There is a reason why ADL + Optane holds world record for single core IOPS:
But obviuosly if one needs real IO setup for VM lab etc, Threadrippers are the way to go due to amount of cores and lanes. Just that not everyone needs so much, and ADL serves so many roles so well.
 
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lightmanek

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Feb 19, 2017
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I don’t know what numa options Threadripper have due to only 4 channel memory. I deal with Epyc processors at work though. They have several options due to the distributed L3 cache and the IO die being divided into quadrants. You can set it to treat each L3 cache as a separate numa domain. You can also split it by the IO die quadrants, which effects how the memory is interleaved. NPS1 (Numa per socket) will result in 1 numa node with memory interleaved across all 8 channels. NPS2 will have 2 domains per socket, each with memory interleaved across 4 channels. The NPS4 setting is each quadrant is a separate domain with memory interleaved across 2 channels.

Do Threadripper CPUs have some of these settings or only game mode?
Yes, AsRock X399 board I had gave all the NUMA options in the BIOS.
 

JoeRambo

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Jun 13, 2013
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Not anymore with the new Spectre BHI, lol.
Frankly those IOPS matter the most in the systems that are already running with mitigations=off. And i expect the impact of mitigations to soften with time, just like original Meltdown stuff, that was ridiculous at start and then softened with new compiler options and kernel support.
 

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