Thoughts on "8 Core" Bulldozer and "4 Core Sandy Bridge"

[bronxzv]

The Vex Prefix is Intels Mitosis

nope, these are two fully orthogonal issues

VEX is simply the prefix for all AVX instructions used by x86 CPUs like Intel Core i7 2600, etc.

 

[Nemesis 1]

For your information the VEX prefix is *already used* for today's AVX as featured in Sandy Bridge and in forthcoming AMD's Bulldozer. So basically all your lengthy talk about the "prefix of vex" (sic) hinting at some non-x86 future is pure BS. Hint: the only goal of prefixes (such as REX in the past) is to extend the x86 ISA, if it was a new ISA no prefix will be needed and the code will be yet more dense.

Only on an AMD XOD prefix . Rex in a SB vexprefix is in the Vex prefix this is called a pre computatain slice or a P-slice . You need to supply a link to go with what your saying . I have done that . Your either trolling or your reading comprehension is very low.

GEt links to back your argument . I have. The rex prefix inside the vexprefix is = to mitosis . I can prove that with the information in this thread. Now go get facts to back up your empyty words or stop trolling .

 

[Nemesis 1]

nope, these are two fully orthogonal issues

VEX is simply the prefix for all AVX instructions used by x86 CPUs like Intel Core i7 2600, etc.

Link or stop trolling . The PDF shows exactly what the Vex prefix is . Its intels PDF Intel invented AVX Intel invented the Vex prefix .

 

[bronxzv]

Link or stop trolling .

I'm not trolling, so nothing to stop I suppose...
anyway, here is a link for you: http://en.wikipedia.org/wiki/VEX_prefix

The PDF shows exactly what the Vex prefix is . Its intels PDF Intel invented AVX Intel invented the Vex prefix .

Indeed Intel defined AVX and the VEX prefix and AMD adopted it for Bulldozer (much as AMD defined REX and Intel adopted it for Prescott), it's completely unrelated with Mitosis, though.

 

[Nemesis 1]

nope, these are two fully orthogonal issues

VEX is simply the prefix for all AVX instructions used by x86 CPUs like Intel Core i7 2600, etc.

It doesn't matter what you say all the info is in this thread real facts you joined this forum under another name or otherwise just for this thread for reason that are obvious .

You really need some facts to back up your claim . I have all the debates points as it is already. You need to show facts as I have .

 

[Nemesis 1]

I'm not trolling, so nothing to stop I suppose...
anyway, here is a link for you: http://en.wikipedia.org/wiki/VEX_prefix



Indeed Intel defined AVX and the VEX prefix and AMD adopted it for Bulldozer (much as AMD defined REX and Intel adopted it for Prescott), it's completely unrelated with Mitosis, though.

AMD has rights only to the AVX instruction set . Not the code and software to optimize for it . I will say this One more Time the VEXPREFIX = Mitosis and is infact Mitosis . Renamed from its research name to its realworld usage name .

 

[Nemesis 1]

I'm not trolling, so nothing to stop I suppose...
anyway, here is a link for you: http://en.wikipedia.org/wiki/VEX_prefix



Indeed Intel defined AVX and the VEX prefix and AMD adopted it for Bulldozer (much as AMD defined REX and Intel adopted it for Prescott), it's completely unrelated with Mitosis, though.

A link to AMD name rex in SSE2. Didn't happen

 

[bronxzv]

You need to show facts as I have .

well, here is a link for you: http://en.wikipedia.org/wiki/VEX_prefix

 

[bronxzv]

I will say this One more Time the VEXPREFIX = Mitosis and is infact Mitosis . Renamed from its research name to its realworld usage name .

care to provide us a source for this scoop?

 

[Nemesis 1]

Your link is already in this thread 2 times plus that info is pasted in here also . YOU PROVE THAT AMD CAN USE THE VEXPREFIX . The fact that AMD uses the XOP prefix says it all . They are not the same . There are no P-Slices in XOP

 

[bronxzv]

The fact that AMD uses the XOP prefix says it all . They are not the same .

FYI AMD's XOP *use the VEX prefix*, both AVX, FMA4 and XOP use the VEX prefix in Zambezis CPU which are sampling *now*

just look at this link for more detailed information: http://en.wikipedia.org/wiki/VEX_prefix

 

[Nemesis 1]

Its already posted here Read be informed befor debating . The Mitosis PDf has no link you need to google intel mitosis . A smart guy such as yourself should have no trouble funding it is the 3 rd or forth down from google page .I copied it all long long ago in a galaxy not far away. The PrefixVex is in 2 differant PDFs already posted here . 1 is 800 pages the other is 500 pages . When ya read the info come back say in 6 months we can finish the debate till than stop trolling .

 

[Nemesis 1]

FYI AMD's XOP *use the VEX prefix*, both AVX, FMA4 and XOP use the VEX prefix in Zambezis CPU which are sampling *now*

just look at this link for more detailed information: http://en.wikipedia.org/wiki/VEX_prefix

Prove that with your link Copy and paste your proof . LOL at YOU. Not the whole link just the part that says AMD can use Vex prefix. AMD doesn't have the compilers to do Mitosis and never will have .

 

[bronxzv]

The Mitosis PDf has no link

indeed, it has no link, even not a very remote one, with the VEX prefix,

for help understanding VEX just have a look here: http://en.wikipedia.org/wiki/VEX_prefix

 

[bronxzv]

AMD doesn't have the compilers to do Mitosis and never will have .

Portland you mean? or gcc? or vc++? Indeed, it's well possible that they don't care, frankly each time I tried the speculative precomputation thingy in ICC (sequels of Mitosis) the speedups were very deceptive, maybe you are luckier than me, which speedup do you get? with which version of ICC?

 

[Nemesis 1]

IF you want to understand prefix of VEX Read the 500 /8oo page INTEL pdf. I still waiting for your copy paste . Why you spreading disinformation is unknown to me ,but logic tells me its ugly.

 

[Nemesis 1]

It's well possible, frankly each time I tried the speculative precomputation thingy in ICC (sequels of Mitosis) the speedups were very deceptive, may be you are luckier than me, which speedup do you get? with which version of ICC?

That information is not available to you . So you have a mitosis compiler? NOT likely.

 

[Riek]

Your link is already in this thread 2 times plus that info is pasted in here also . YOU PROVE THAT AMD CAN USE THE VEXPREFIX . The fact that AMD uses the XOP prefix says it all . They are not the same . There are no P-Slices in XOP

AMD cannot ADD things to the VEX prefix, it can USE the VEX prefix for instructions defined by intel. e.g. AVX or AVX2 in the future.

Ofcourse AMD can optimize software for their implementation of instructions that are located in the VEX prefix. Those are 2 completely different things.

 

[Nemesis 1]

indeed, it has no link, even not a very remote one, with the VEX prefix,

for help understanding VEX just have a look here: http://en.wikipedia.org/wiki/VEX_prefix

Idon't care about vectors only the prefix VEX

 

[Nemesis 1]

AMD cannot ADD things to the VEX prefix, it can USE the VEX prefix for instructions defined by intel. e.g. AVX or AVX2 in the future.

Ofcourse AMD can optimize software for their implementation of instructions that are located in the VEX prefix. Those are 2 completely different things.

No they cann't . VEXprefix is Mitisis as defined in the mitosis absract and also in the Vexprefix abstract also defines Vex prefix they are defined the same . I will pull and paste what you need to understan mitosis .

 

[bronxzv]

That information is not available to you . So you have a mitosis compiler? NOT likely.

ICC provides "Software-based Speculative Pre-Computation" since the version 9.0, we are at v12.0 update 4 now

 

[Arachnotronic]

...could we stop talking about the prefix VEX?

Intel can't lock AMD out of instructions. That is all.

 

[Nemesis 1]

Intel is not locking AMD out of AVX instruction set . prefixVEX is code with P-slices it requires software .

This is The prefixVEX = Mitosis .


value prediction. The
synchronization approach imposes a high overhead when
dependences are frequent, as in the workload presented here.
Value prediction has more potential – if the values that are
computed by one thread and consumed by another can be
predicted, the consumer thread can be executed in parallel with
the producer thread since these values are only needed for
validation at a later stage. It is typically assumed that these value
predictions are computed in hardware. The Mitosis system
presents a novel approach, which adds code (derived from the
original program) to predict in software the live-ins (values
consumed, but not produced by, the thread) for each speculative
thread. Because mechanisms for recovery of incorrect threads are
already in place, the code to produce the values need not always
be correct, and can be highly optimized. We refer to this code as
pre-computation slices (p-slices). The main advantages of p-slices
are: (1) they are potentially more accurate in the prediction of
live-ins than a hardware-based predictor, since it is derived from
the original code, (2) they can encapsulate multiple control flows
that contribute to the prediction of live-ins, and (3) they can
accelerate the detection of incorrectly spawned threads.

AMD has No rights to this under any agreements ./


Now if you want I will get the vexprefix using rex prefix inside the Vexprefix and you will clearly see Vex prefix are P-slices SOFTWARE compilers . AMD hasn't and will never have this its intel patent.

 

[bronxzv]

VEXprefix is Mitisis as defined in the mitosis absract I will pull and paste what you need to understan mitosis .

I'll be immensely glad if you post an exact excerpt of a real document establishing a link between VEX and Mitosis, please do it!

 

[bronxzv]

value prediction. The
synchronization approach imposes a high overhead when
dependences are frequent, as in the workload presented here.
Value prediction has more potential – if the values that are
computed by one thread and consumed by another can be
predicted, the consumer thread can be executed in parallel with
the producer thread since these values are only needed for
validation at a later stage. It is typically assumed that these value
predictions are computed in hardware. The Mitosis system
presents a novel approach, which adds code (derived from the
original program) to predict in software the live-ins (values
consumed, but not produced by, the thread) for each speculative
thread. Because mechanisms for recovery of incorrect threads are
already in place, the code to produce the values need not always
be correct, and can be highly optimized. We refer to this code as
pre-computation slices (p-slices). The main advantages of p-slices
are: (1) they are potentially more accurate in the prediction of
live-ins than a hardware-based predictor, since it is derived from
the original code, (2) they can encapsulate multiple control flows
that contribute to the prediction of live-ins, and (3) they can
accelerate the detection of incorrectly spawned threads.

ICC with the -ssp compilation flag do the slicing you are refering to since several years
http://www.ncsa.illinois.edu/UserInfo/Resources/Software/Intel/Compilers/9.0/C_ReleaseNotes.htm

VEX encoding wasn't involved and it has (obviously) a completely different purpose