Originally posted by: redhatlinux
Does ANYBODY in this forum understand pipeline design, branch prediction, cache schemes etc .. I am an AMD DIEHARD, but running on a Hyper-threading P4 right now. THE P4 clock can run fast because the pipe is SOOOOO long it does almost nothing each cycle. When the pipe steps VERY frequently, the pipe is filled with NOPs (dummie ops blazing away at this high gig speed). A Cache miss on P4 is like DEATH. Translation for those who don't know, high speed, little work per cycle. Lower speed, more work per cycle, much better cache scheme, better pipe design etc etc AMD. BENCHMARKS ARE BULLSH!T. I have re-written, some of IBM's code in the past and gotten a 15% improvement. At pretty much zero cost.
Now to the TOPIC, AMD has VERY small margins, they pretty much sell EVERYTHING they can make and OBTW, the FEDS,

( can't say any more, CLASSIFIED), use lots of AMD64 chips