theoretical peak gigaflops

[CTho9305]

Anyone got the numbers for the different procs? P3 1gig, athlon 1gig, tbird 1 gig, mp/xp 1 gig, p4 underclocked to 1gig, g4 overclocked to 1 gig, various sun processors at 1 gig, various alphas at 1 gig, and a 386 at 1gig? 😀

just wondering, since apple is the only one that advertises flops a lot.

It should be easy to calculate... find the clock cycles for the shortest flop (add? move?), multiply by number of pipeline stages and number of fpu pipelines? or something like that?

 

[RedBeard0531]

forget the 386, Thinck of what a TI-92+(high-end Graohing calc) can do at 1GHz😉

on topic: Are you going to include SSE type instructions. I also don't think it's fair to standerdize the clk. They should all be tested at their own max.

 

[BurntKooshie]

P3/athlon's have flops of 4gflops, of course, that's with SIMD. I think the same for the P4 (underclocked).

 

[CTho9305]

yeah, i wanted to include SIMD. got a source for those #'s?

 

[BurntKooshie]

Both can basically do 4 FP SIMD instructions every cycle.

 

[CTho9305]

how about if you also use the integer units to emulate an fpu? 😀 come on, find me a way to market an x86 chip as capable of more flops than a mac! 😉

 

[CTho9305]

how about a 386? IIRC an integer divide is at best 14 clock cycles 😀

 

[BurntKooshie]

Divides take longer than other ops 🙂

If, however, you wanted to calculate the mflops of a 386 at 1ghz doing divides, it'd be (1 billion cycles/second) * (14seconds/ "flop") and you'd get the peak flops, because it was a scalar, non-pipelined design. Yikes flops are useless 😉

 

[CTho9305]

yep 😉