I'll keep posting this link as it appears too many of us are misinformed.That was the point I was making; the only way it would work would be if the controller was on-die with the eDRAM and communicated with the CPUs over Infinity Fabric, in which case it'd hardly be any better than going to main memory. A proper controller wouldn't add too much die space, but obviously it's something that would have to be added in Zen's successors.
(Of course, in an ideal world AMD would fill the space with a nice big HBM2 cache, but even if the necessary controller logic was there I shudder to think how much the required interposer would cost)
Shall we say roughly $3.
A 200mm^2 APU die + a 100mm^2 HBM2 stack.
http://electroiq.com/blog/2012/12/lifting-the-veil-on-silicon-interposer-pricing/
"Sesh Ramaswami, managing director at Applied Materials, showed a cost analysis which resulted in 300mm interposer wafer costs of $500-$650 / wafer. ----------- Since one can produce ~286 200mm2 die on a 300mm wafer, at $575 (his midpoint cost) per wafer, this results in a $2 200mm2 silicon interposer."