I'm aware. After this I actually intend to lower my overclock to 4.4 for 24/7 use because it's at a significantly lower voltage (that's where I hit my "wall" where things went somewhat exponential) and because the performance difference is minimal.
It's not really something you have a choice about though, it's simply not going to be stable at a 4600MHz cache speed. Not happening. I wasn't able to get 4400MHz at 1.330vCache, and I refuse to go any higher on vCache because I consider those voltages to be of higher risk than vCore. Considering the default speed of the cache is 3400MHz and I'm running at 4000MHz, it's still 600MHz faster than it otherwise would be and less of a delta with the core.
All that said, it seems it's irrelevant. Using the optimized linpack I am unable to get stable at 4.6 at voltages I would even remotely deem acceptable for that clock speed. I can keep ramping voltage, but I noticed an irregularity that concerns me so I'm going to postpone further benchmarking until I can analyze that further. Here's the data I have so far:
4.6@1.385vCore
Peak 76/84/83/78 (this is the irregularity btw, the core-to-core delta should be much smaller considering I've delidded and have lapped my IHS and waterblock, I think I may have somehow not gotten enough CLU on in a spot or the IHS is very not flat on the underneath inside the area that sits over the die).
Code:
Intel(R) Optimized LINPACK Benchmark data
Current date/time: Sun Feb 09 06:19:32 2014
CPU frequency: 4.598 GHz
Number of CPUs: 1
Number of cores: 4
Number of threads: 4
Parameters are set to:
Number of tests: 12
Number of equations to solve (problem size) : 1000 2000 3000 4000 5000 10000 15000 20000 25000 30000 35000 40000
Leading dimension of array : 1000 2000 3000 4000 5000 10000 15000 20000 25000 30000 35000 40000
Number of trials to run : 4 4 4 4 4 2 2 2 2 1 1 1
Data alignment value (in Kbytes) : 4 4 4 4 4 4 4 4 4 4 4 4
Maximum memory requested that can be used=4210869504, at the size=40000
=================== Timing linear equation system solver ===================
Size LDA Align. Time(s) GFlops Residual Residual(norm) Check
1000 1000 4 0.017 40.0328 1.083189e-012 3.693953e-002 pass
1000 1000 4 0.011 63.0760 1.083189e-012 3.693953e-002 pass
1000 1000 4 0.005 122.7537 1.083189e-012 3.693953e-002 pass
1000 1000 4 0.005 123.6466 1.083189e-012 3.693953e-002 pass
2000 2000 4 0.040 134.0015 4.220901e-012 3.671667e-002 pass
2000 2000 4 0.040 134.8228 4.220901e-012 3.671667e-002 pass
2000 2000 4 0.039 138.4833 4.220901e-012 3.671667e-002 pass
2000 2000 4 0.038 138.8564 4.220901e-012 3.671667e-002 pass
3000 3000 4 0.123 146.0860 1.016483e-011 3.914231e-002 pass
3000 3000 4 0.114 157.3810 1.016483e-011 3.914231e-002 pass
3000 3000 4 0.115 157.2500 1.016483e-011 3.914231e-002 pass
3000 3000 4 0.114 158.6057 1.016483e-011 3.914231e-002 pass
4000 4000 4 0.253 168.7408 1.906425e-011 4.155234e-002 pass
4000 4000 4 0.252 169.4226 1.906425e-011 4.155234e-002 pass
4000 4000 4 0.251 170.2759 1.906425e-011 4.155234e-002 pass
4000 4000 4 0.257 166.3512 1.906425e-011 4.155234e-002 pass
5000 5000 4 0.477 174.7770 2.299338e-011 3.206242e-002 pass
5000 5000 4 0.470 177.4455 2.299338e-011 3.206242e-002 pass
5000 5000 4 0.470 177.3550 2.299338e-011 3.206242e-002 pass
5000 5000 4 0.471 176.9655 2.299338e-011 3.206242e-002 pass
10000 10000 4 3.264 204.2947 9.420734e-011 3.321846e-002 pass
10000 10000 4 3.257 204.7249 9.420734e-011 3.321846e-002 pass
15000 15000 4 10.476 214.8195 2.137378e-010 3.366406e-002 pass
15000 15000 4 10.481 214.7155 2.137378e-010 3.366406e-002 pass
20000 20000 4 23.507 226.9138 3.723286e-010 3.295924e-002 pass
20000 20000 4 23.502 226.9643 3.723286e-010 3.295924e-002 pass
25000 25000 4 46.011 226.4214 5.678848e-010 3.229357e-002 pass
25000 25000 4 46.048 226.2407 5.678848e-010 3.229357e-002 pass
During these runs the highest GFLOPs I saw was 231, however in all tests around the time it hits the 30000 or 35000 problem size I end up getting the watchdog timer BSOD.