The P5 where is it and what you want on it

[Acanthus]

Read up on Meram, it is likely to be the "Pentium 5"

 

[phaxmohdem]

Sorry just another random thought. Isn't "Pentium 5" kind of redundant?

 

[imported_Kensai]

I want a CPU with multiple cores and at least 2GB of L1 cache.

 

[Sentential]

They pushed conroe foreward to Q2 2006. It wont have an ondie-controller but it should be pretty damn good.

Most likely they will go with Pentium5 once they swap sockets with Merom.

 

[Gamingphreek]

2gig of SRAM. First of all it would be insanely slow, and second of all it would be well over $5000. Just for the record... i know you are kidding but i didn't want anyone getting ideas.

-Kevin

 

[Fox5]

Originally posted by: Soccerman06
From what I've seen with the Pentium brand and other major manufactures (IBM, AMD ect) is it takes anywhere from 3-7 years to make a new core from scratch. I also remember that my old P2 OCed almost 30% over it's stock speed (from 350mhz-450mhz). But that was when Pentium made too many of the P2 450mhz proc and downclocked some to 350mhz. I was one of the lucky ones who get a hand-me-down 450mhz.

You cant say that the PentiumM/Centrino is the next gen core because its a reworked P3. So in reality its a P3.5. I just had to say that since I know a lot of people who love the P-M and think its Pentiums next-gen CPU.

That all being said, Pentium is overdue for another core, its been awhile and it better live up to the expectations of everyone and deliver on lower heat generation, not necessarily a higher clock speed, but faster overall performance, and to be able to work in tandem with other cores (multi-core) just like the A64.

Why can't I say it's next gen? The differences from P3 to PM are much greater than even Pentium Pro to Pentium 3. Athlon to Athlon 64 was K7 to K8, and Northwood to Prescott was also a generational change...
I see PM as an equal generation as the original P4, some improvement to the PM is the next gen after that, then it should have 1 morearound the time AMD is moving onto K10. I don't think the underlying core needs significant revisions to calculate as a next gen processor.

 

[HDTVMan]

Half Pepperoni and Half Sausage. Hopefully it wont be 120watts.

I would like Low Cooling obviously.

 

[Maximilian]

They should make the P5 or whatever they call it a...... TRIANGLE!! Yes... now whos seen a processor that isnt a sqaure/rectangle huh? Imagine the marketing! "THE ONLY 3 SIDED PROCESSOR ON THE MARKET!! BUY HERE!!" Amazing

 

[miketheidiot]

I would like to see someone make a wide and long piped core. There is no reason imo why there can't be a 3-4 pipe processor with pipeline in the 15-20 range. I don't understand how a longer pipe leads to slow IPC as many seem to hint at. What they should be thinking is that the longer pipe allows for higher clockspeed which = higher performance.

 

[phaxmohdem]

Re: to miketheidiot

You will have to find a nice article aout piplining and the way a processor works. There are several of them out there, they are long but interesting (though technical) reads. I'm not so sure that central CPU's have multiple pipes.... Perhaps you are confusing a GPU (which has many pixel/vertex pipelines to get more work done in parralell... similar to multicore thinking).

Super-Simplified version of pipelining...
Pipelining is a processors "assemnly line" it gets the command from the user or program, and starts its journey through the various stages of its journey before it gets output as the final result. A processor such as the Northwood P4 for example has 20 stages in its pipeline (Prescott has 31) In order to keep instructions moving as quickly as possible through CPU, when an instruction goes from stage 1 to stage 2 lets say, another instruction in line behind it pops into stage 1 for processing. this way theoretically up to 20 instructions could be processed at the same time filling all stages of the pipe. The problem with this however lies in the fact that sometimes an instruction gets sent to the wrong place by the Branch Prediction unit, which means that EVERY instruction that is currently loaded in the pipeline must be flushed, and the process must be started over again from the instruction that failed on back. These branch misses cause the pipeline to stall, resulting in not as many instructions per clock cycle.

That is a VERY VERY simple version of the story. again, if you want to really know how it works, find a good article online about the subject, grab a snack and read for a while.

 

[Fox5]

I think he's referring to the number of execution units when he says pipes.

Anyhow, Athlon has 3 execution units, and I believe Athlon 64 has a 14 stage pipeline.

IBM's G5 I think had 4 execution units(or something equivilent) and a Northwood-esque pipeline, yet it performs far worse than even an athlon xp in just general number crunching unless altivec is used, and has always clocked within 100mhz of whatever the latest athlon is doing.(at one point athlon 64 was at 2.4ghz, and the G5 was at 2.5ghz, now the athlon 64 is at 2.8ghz and the G5 at 2.7ghz....and releasing a heck of a lot more heat)

Now then, Pentium M has less execution units and a shorter pipeline, yet people are managing to overclock it to northwood levels with enough cooling, still in absolute terms they seem to max out about the same.

 

[Gamingphreek]

The P-M does not have a shorter instruction pipeline than the A64. It is put somewhere between the A64 and the AXP. We do not know where because Intel will not release the specs.

-Kevin

 

[Fox5]

Originally posted by: Gamingphreek
The P-M does not have a shorter instruction pipeline than the A64. It is put somewhere between the A64 and the AXP. We do not know where because Intel will not release the specs.

-Kevin

The A64 has a longer pipeline than the AXP, so I don't know how you can say the P-M is longer than the A64 but shoter than the AXP.

 

[BitByBit]

Refering to processors as having 'multiple pipes' is just another way of saying it has multiple execution units.
It is the number of execution units that determines the theoretical maximum IPC of that processor, and not pipeline depth. Increasing pipeline depth does indeed increase the impact of pipeline flushing in terms of wasted clock cycles, but when combined with an accurate branch predictor, the pipeline depth of a processor can be extended without a significant effect on IPC.
When the pipeline is full, the IPC is no different to that of shallower-pipelined designs, since one or more instructions are being completed per clock.

Dothan's pipeline depth is thought to be around 12 stages, as it is with the Athlon 64.

 

[TGS]

Originally posted by: Fox5

Originally posted by: Soccerman06
Ok people i donno if this has been talked about before or not but what do yall want on it and what is going to be on it in reality (Yonah and multi-cores dont count).

I pesonally am hoping for an on-die memory controller, better (and less) mobo, better SLI, fully unlockable for OCing, much, much less heat dissapation.

I would like to see on the mobo an easy adaption for water cooling and possibly a PPU.

Umm, most of those things you listed have nothing to do with the cpu.

Noticing those two, an inclusion of either should seriously help the Intel cpu situation.

Even with AMD blinders on (not really, it's just been the better Bang-for-the-Buck? for me) if Intel gets a integrated memory controller, AMD will be hurting onthe performance side.

 

[BitByBit]

Not necessarily.
The Athlon needed a faster memory interface. The main reason the 'C' revision P4 dominated the XP in gaming was due to its faster memory interface. Thus, the P4 would not benefit from an IMC like the Athlon did.
If you look here you will see that the K7 was at a massive disadvantage in this respect.
Dothan on the other hand doesn't actually need a fast memory interface in the same way that the P4 and Athlon do. It was designed from the ground up to limit memory access as much as possible, since memory access consumes alot of power.
If Dothan were to use an IMC, it would certainly benefit, but not by as much as people may be tempted to think, largely thanks to its huge L2 reducing the need for memory access.

 

[Fox5]

Originally posted by: BitByBit
Not necessarily.
The Athlon needed a faster memory interface. The main reason the 'C' revision P4 dominated the XP in gaming was due to its faster memory interface. Thus, the P4 would not benefit from an IMC like the Athlon did.
If you look here you will see that the K7 was at a massive disadvantage in this respect.
Dothan on the other hand doesn't actually need a fast memory interface in the same way that the P4 and Athlon do. It was designed from the ground up to limit memory access as much as possible, since memory access consumes alot of power.
If Dothan were to use an IMC, it would certainly benefit, but not by as much as people may be tempted to think, largely thanks to its huge L2 reducing the need for memory access.

That might hold true, except the 939 cpus still get a decent benefit from dual channel, so P4s probably would too. Dothans probably wouldn't as they currently recieve no benefit from 533mhz ddr2 or dual channel. BTW, I see the large L2 cache of dothan as an almost "instead of" to the memory controller.

Anyhow, I see the integrated memory controller as more of a solution for multicpu performance than single cpu. Multicpu is the future, AMD knew it, and the IMC seems to contribute greatly to it. Dual core AMD chips perform better than expected because of it, and multi cpu AMD systems benefit from increased bandwidth with every added chip.