Discussion The beauty of AMD chiplet design

[Kocicak]

I have not seen this discussed before. Beside all the obvious advantages of the chiplet design, there is one more thing: the current 8 core chiplet will be relevant and usable for two or even three years. I believe that even that far in future it will be usable in some low end processors or other applications. The same little universal 8 core chiplet produced in so high volume allowing the development cost to be disolved so much, that overall it will be extremelly cheap to produce.

Why not to split the consumer processor line in two parts: one higher end part, which would be getting new generation chiplets every time they are released, and lower end processors, which would have the computing unit updated for example every second year? I believe it would be very cost effective way and it would really allow the consumers to enjoy the benefits of the design and high volume (and therefore low cost) production.

 

[piesquared]

Does AMD's cache subsystem still perform better than intel's? Lower latency and higher bandwidth?

 

[amd6502]

Shows latency minimizing effect of the larger L3 offset by slightly higher RAM access time

 

[DrMrLordX]

Shows latency minimizing effect of the larger L3 offset by slightly higher RAM access time

That's not guaranteed though, since we don't know that the two systems on the graphs had the same memory timings or clockspeed. Tighter memory timings would give us a different graph for Zen2. It does show us that L3 has effectively doubled over Zen+ with impressive results.

 

[Atari2600]

If this is real there's a significant latency improvement between ~6 and ~24MB, while beyond that it's slightly worse (though the graph does a lot of stupid interpolation, it would be worth more knowing the exact data points).

The "beyond being slightly worse" will be very dependent on the speeds/timings that the memory controller can run at... which of course for an ES is likely not going full bore or anything like it!