This post is about the 1/5 and 2/5 dividers at high FSB for the PCI and AGP speeds on the 8KHA+.
I've read all the posts on the 8KHA+ and heard the Epox official response, but I'm still not convinced about there being no higher dividers at high FSB.
I?m no motherboard electrical engineer (wish we had one in this thread
), but I?m sure this is how frequency is selected.
Let?s start with the 200/266fsb jumper. We all know that some CPU?s will run at 200 and others 266 FSB.
Upon powering the system, the clock generator provides a frequency to the CPU in order to get it to work. The frequency it sends is selected via a hardware jumper on the board. If this frequency is wrong, the next step of programming the clock gen can?t commence.
The CPU along with the bios settings are now used to program the clock generator that provides our bus frequencies. The bios knows what signals to send to the clock generator to produce the FSB you select, but has no ability to select a given divider as this is done automatically depending on the functionality mode needed. As far as I know, the chipset does not play a part in selecting the frequencies; it only has to be able to run at them
Functionality Modes for the clock Gen
The above table shows the various functionality modes available from the clock gen for a given master frequency (the FSB).
The master frequency of the CPU is selected in the bios (100-200 FSB). This setting is then sent to the clock gen (say 160), which selects a functionality mode and either subtracts 1-7 Mhz or adds 1-9 Mhz to get the required speed.
In this case it would select the 166.67 mode and subtract 7 Mhz to get 160. It then hands this master frequency (160) to various dividers internally, which divide the frequency down more for the various bus speeds in accordance to the functionality mode selected.
Since the clock gen has selected 166.67 functionality mode for our 160 setting, we should get the 1/5 and 2/5 dividers being used and PCI speeds of 32 and AGP speeds of 64 going by the spec sheet.
Therefore we should be seeing the dividers kick in at 160 FSB, as it?s using the 166.67 functionality mode and subtracting 7 Mhz. As far as I can tell, the dividers are automatically selected with the functionality mode and there is no way to manually enable/disable the dividers.
This is the theory surrounding this topic pointing towards the dividers being present, but to be sure we need to use an oscilloscope. A guy named Brad has done just that, and claims to have confirmed the above theory but we need more results just to be sure. Any offers?
As long as you can get the bios to post, the clock gen should have been programmed and can be tested by using the following pins:
11
13
14
16
17
18
20
21
Other connector has to be ground.
You may have problems with the probe being too large, in which case a pin connected to it should help.
I've read all the posts on the 8KHA+ and heard the Epox official response, but I'm still not convinced about there being no higher dividers at high FSB.
I?m no motherboard electrical engineer (wish we had one in this thread
), but I?m sure this is how frequency is selected.Let?s start with the 200/266fsb jumper. We all know that some CPU?s will run at 200 and others 266 FSB.
Upon powering the system, the clock generator provides a frequency to the CPU in order to get it to work. The frequency it sends is selected via a hardware jumper on the board. If this frequency is wrong, the next step of programming the clock gen can?t commence.
The CPU along with the bios settings are now used to program the clock generator that provides our bus frequencies. The bios knows what signals to send to the clock generator to produce the FSB you select, but has no ability to select a given divider as this is done automatically depending on the functionality mode needed. As far as I know, the chipset does not play a part in selecting the frequencies; it only has to be able to run at them
Functionality Modes for the clock Gen
The above table shows the various functionality modes available from the clock gen for a given master frequency (the FSB).
The master frequency of the CPU is selected in the bios (100-200 FSB). This setting is then sent to the clock gen (say 160), which selects a functionality mode and either subtracts 1-7 Mhz or adds 1-9 Mhz to get the required speed.
In this case it would select the 166.67 mode and subtract 7 Mhz to get 160. It then hands this master frequency (160) to various dividers internally, which divide the frequency down more for the various bus speeds in accordance to the functionality mode selected.
Since the clock gen has selected 166.67 functionality mode for our 160 setting, we should get the 1/5 and 2/5 dividers being used and PCI speeds of 32 and AGP speeds of 64 going by the spec sheet.
Therefore we should be seeing the dividers kick in at 160 FSB, as it?s using the 166.67 functionality mode and subtracting 7 Mhz. As far as I can tell, the dividers are automatically selected with the functionality mode and there is no way to manually enable/disable the dividers.
This is the theory surrounding this topic pointing towards the dividers being present, but to be sure we need to use an oscilloscope. A guy named Brad has done just that, and claims to have confirmed the above theory but we need more results just to be sure. Any offers?
As long as you can get the bios to post, the clock gen should have been programmed and can be tested by using the following pins:
11
13
14
16
17
18
20
21
Other connector has to be ground.
You may have problems with the probe being too large, in which case a pin connected to it should help.
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