The 480: power consumption, PCI-E powerdraw

[MrTeal]

Facts about PCIe connectors?

https://www.reddit.com/r/Amd/comments/4rbw8p/facts_about_pcie_connectors/

Heh, read several posts up.

 

[William Gaatjes]

I'm curious as to if AMD passed the PCI-SIG Compliance Workshop with the cards that reviewers reviewed, or if something has changed. Would they be required to re-test if a fix is not viable?

I wonder about that too.

A legal work around fix, is to sell the rx480 lower clocked and with less core voltage, to stay within the limits as set by the pci sig group. And allow users to overclock, with a big disclaimer clause that you are fully responsible. No one would care. I mean, how many people do not overclock ? I am very reserved about it and even i have done it a bit.

 

[exar333]

Have a feeling they took a last minute risk by upping the core clocks to gain a performance edge (vs 970) without sufficient re-testing of the power draw. Some spec leaks in weeks before release had the clocks lower than final release.

That's a good point. The way I understood it, the 970 performance was always the goal, as that has been well understood as the 'entry level' VR performance. I also heard about sub 1000mhz clocks as well.

Even if that's the case, I get the sense something didn't work out as well as expected. Be that clocks, IPC or the power consumption.

 

[Stuka87]

I'm curious as to if AMD passed the PCI-SIG Compliance Workshop with the cards that reviewers reviewed, or if something has changed. Would they be required to re-test if a fix is not viable?

My thinking is that some early chips were requiring a higher voltage in order to operate, due to early yielding issues. And because the card is priced so low, throwing away chips was not really an option. By raising that core voltage, even 0.015vdc (the number a lot of guys are under volting by) is enough to put them over spec.

Hopefully as production moves on, this issue goes away. or maybe it already has, and only affected very early chips. This is admittedly a hypothesis without enough data to verify much of it. But certainly seems plausible.

 

[Minkoff]

That's a good point. The way I understood it, the 970 performance was always the goal, as that has been well understood as the 'entry level' VR performance. I also heard about sub 1000mhz clocks as well.

Even if that's the case, I get the sense something didn't work out as well as expected. Be that clocks, IPC or the power consumption.

In order to drive the price down you need, as many chips, as you can get from a wafer.

Without binning (as yo will lose chips) you increase the voltage to qualify them as RX 480. You loose efficiency, but gain in stability.

I guess will see some chips being able to massively underclock why others will have to stay at almost stock voltages. Of course, the GloFo will play a role, as well.

 

[rgallant]

Weird. They've got a whole suite of nice test equipment, why wouldn't they grab a multimeter and just check which source the 12V on the high side switch is connected to in order to actually verify their hunches. It'd take all of 2 minutes.

The neighboring third pin on the top was reserved, but not actually assigned to anything. But now, in the latest standards, it’s generally used as an additional 12V pin, along with the other four, making it possible that a total of five pins are available for the 12V power supply. However, the allowed current was not changed to be compatible with older hardware.

so spec's[amps per pin] are [amps used divided by 4 pins] on the net. = over spec.
new cards use 5 pins the card are with in spec per pin amps lol
http://www.tomshardware.com/reviews...622.html?_ga=1.117291520.727157166.1467521787

sorry MR Teal quoted you by mistake

 

[Despoiler]

It appears you can shift power away from the PCI-E slot and towards PCI-E plug power using nothing but MSI AB. AMD can fix the cards showing anomalous power draw via drivers or BIOS updates.

http://www.overclock.net/t/1604979/...lot-power-draw-for-the-reference-rx-480-cards

http://www.overclock.net/t/1604979/...-for-the-reference-rx-480-cards#post_25320520

So these commands change the default configuration of the IR3567 VRM controller, which is used on all of the reference boards. There are six phases for the GPU power plane (VDDC) and half of these phases are fed from the PCI-E power connector and the other half from the PCI-E slot 12V source. At the default configuration the cards are shipped with, each of the VRM phases handle the same amount of load. The changes made by these commands affect how the load is distributed between the VRM phases.

With the configuration enabled by these commands, the half of the VRM which is fed from the PCI-E power connector will be taking care of a larger portion of the load than the other half. Since the total power draw of the GPU will remain intact, the power draw from the PCI-E slot will decrease and the power draw from the PCI-E power connector will increase.

This will increase the stress on the other half of the VRM, however the operating parameters will still remain safely below any risk limits. The per phase overcurrent limit on these cards is configured extremely conservatively (36A per phase) and even with the changed configuration there is no need to increase these safety limits from their default values. Also the over temperature protection (OTP) limits are left intact (115°C for forced throttling, 130°C for immediate shutdown).

 

[Silverforce11]

@Despoiler

That's because AMD uses a master Mosfet, rated 100A that can dynamically balance the load. This is controllable so the fix should be a simple driver update that signals the Mosfet to load more on the 6pin.

It would still be out of spec if it's drawing more than 150W of the board however.

The best approach is a simple undervolt, lower power usage and removes throttling at the same time.

 

[2is]

Being out of spec by pulling more from the 6pin would be far preferable to pulling it from the PCIe slot IMO.

 

[MrTeal]

@Despoiler

That's because AMD uses a master Mosfet, rated 100A that can dynamically balance the load. This is controllable so the fix should be a simple driver update that signals the Mosfet to load more on the 6pin.

It would still be out of spec if it's drawing more than 150W of the board however.

The best approach is a simple undervolt, lower power usage and removes throttling at the same time.

I'm sorry, but that's just wrong. The low side mosfet is rated at 100A, but you'll never reach that in practice in a synchronous buck converter. Really current rating itself is almost irrelevant in choosing a low side fet, for both of them the most important characteristics are Rds(on) and the gate charge. Generally focus with the low side is given to Rds(on), while low gate charge is the most important parameter for the high side device. Tom's is making the same mistake many people who have a basic understanding of electronics but no practical experience with synchronous buck design and just saying low side current rating * output voltage = max phase power. That's incorrect, and there's lots that limits power before that. Anyway, the selection of the mosfet has nothing to do with balancing the load, and neither the high side or low side are "master" mosfets. Really, if you were to call any the master it would be the high side switch.

The mosfet can't just draw more power from the 6 pin. The proposed solution is to simply disable one of the phases that's attached to the PCIe slot, which will just make a higher percentage of the average current come from the PCIe slot. Unfortunately I don't have a datasheet for the 3567, but the its predecessor the 3566B could only disable the last phase and not an intermediary phase, so they might have gotten lucky that phase 6 is on the slot.

 

[sirmo]

I'm sorry, but that's just wrong. The low side mosfet is rated at 100A, but you'll never reach that in practice in a synchronous buck converter. Really current rating itself is almost irrelevant in choosing a low side fet, for both of them the most important characteristics are Rds(on) and the gate charge. Generally focus with the low side is given to Rds(on), while low gate charge is the most important parameter for the high side device. Tom's is making the same mistake many people who have a basic understanding of electronics but no practical experience with synchronous buck design and just saying low side current rating * output voltage = max phase power. That's incorrect, and there's lots that limits power before that. Anyway, the selection of the mosfet has nothing to do with balancing the load, and neither the high side or low side are "master" mosfets. Really, if you were to call any the master it would be the high side switch.

The mosfet can't just draw more power from the 6 pin. The proposed solution is to simply disable one of the phases that's attached to the PCIe slot, which will just make a higher percentage of the average current come from the PCIe slot. Unfortunately I don't have a datasheet for the 3567, but the its predecessor the 3566B could only disable the last phase and not an intermediary phase, so they might have gotten lucky that phase 6 is on the slot.

Someone mentioned that the particular controller 3567 allows for fine control of mosfet ratios, where they could leverage this to change the distribution [less from PCIE bus more from 6-pin]. Technically it could be possible by varying the duty cycle of the Mosfets. Just not sure if this controller allows for that. The datasheet is nowhere to be found.

edit: whoops I think I may have found it: [PDF warning] http://www.infineon.com/dgdl/pb-ir3567b.pdf?fileId=5546d462533600a4015356803a7228ef

Ok that datasheet doesn't provide enough information, but it does say that phases can be dropped and added:

IR’s Dynamic Phase
Control adds/drops active phases based upon load
current and can be configured to enter 1-phase
operation and diode emulation mode automatically or
by command.

Ok so I did further research, this is on the older 3565b http://www.irf.com/product-info/datasheets/data/ir3565b.pdf

Page 41:

So they could configure DPC so that one the PCIE-bus phases is off until extreme scenarios call for it to be on (like overclocking). And balance the current draw that way.

 

[Wall Street]

Someone mentioned that the particular controller 3567 allows for fine control of mosfet ratios, where they could leverage this to change the distribution [less from PCIE bus more from 6-pin]. Technically it could be possible by varying the duty cycle of the Mosfets. Just not sure if this controller allows for that. The datasheet is nowhere to be found.

Over at another forum they have started toying with a BIOS to make the PCIe draw more than the motherboard connector. The PCPer guys have tested it with some success.

 

[sirmo]

Cheers will keep an eye on it.

 

[MrTeal]

Someone mentioned that the particular controller 3567 allows for fine control of mosfet ratios, where they could leverage this to change the distribution [less from PCIE bus more from 6-pin]. Technically it could be possible by varying the duty cycle of the Mosfets. Just not sure if this controller allows for that. The datasheet is nowhere to be found.

edit: whoops I think I may have found it: [PDF warning] http://www.infineon.com/dgdl/pb-ir3567b.pdf?fileId=5546d462533600a4015356803a7228ef

Ok that datasheet doesn't provide enough information, but it does say that phases can be dropped and added:



Ok so I did further research, this is on the older 3565b http://www.irf.com/product-info/datasheets/data/ir3565b.pdf

Page 41:

So they could configure DPC so that one the PCIE-bus phases is off until extreme scenarios call for it to be on (like overclocking). And balance the current draw that way.

Well, there's two things. You can drop and add phases realtime, but that is an automatic thing that the VRM controls. You can also set the max number of phases, which will limit the VRM to only use phases 1 to #max number of phases. Unfortunately, if the phase layout in Wall Street's link is correct, that does help us at all as phases 5-6 are on the PCIe power plug and phases 1-4 are on the slot.
Unfortunately with the VRMs based on the Comanche core (3565, 3566 and 3567) you can't selectively choose phases. I've verified this over email with an application engineer from IR as I had an application where I wanted to run phases 1,3,5 and turn off phases 2,4 and 6 on an IR3566B. It was physically impossible and I ended up having to sub-optimally disable 4-6 and leave 1-3 running.
The other thing is that you can't select the number of phases in real time. You can set the auto phase adjusting parameters and select the max number of phases, but you can't edit the max number of phases while the rail is active (IE, while GPU core voltage is applied). Essentially that means you can't edit that limit while the GPU is on.

Edit again: There's been a further update. Someone mentioned that the fix edits registers 0x1E and 0x1F. 0x1E[7:4] control phase 1 gain, 0x1E[3:0] control P2 gain, and 0x1F[7:4] control phase 3 gain. It looks like they're increasing gain on the PCI 6 pin plug to try and force the controller to allocate more current to the 6 pin plug.

 

[Silverforce11]

New driver coming, fixes power issue as well as improve performance.

 

[beginner99]

New driver coming, fixes power issue as well as improve performance.

AMD will never learn. If they can churn out a new driver with these fixes why didn't they do it before the release? Now the RX 480 already has a bad rep just like 290 did and reviews are done. Any performance increase will not be seen by people looking at reviews. Plus a press release with a typo: 3%1. hat is that supposed to mean? 31%?

 

[sirmo]

Well, there's two things. You can drop and add phases realtime, but that is an automatic thing that the VRM controls. You can also set the max number of phases, which will limit the VRM to only use phases 1 to #max number of phases. Unfortunately, if the phase layout in Wall Street's link is correct, that does help us at all as phases 5-6 are on the PCIe power plug and phases 1-4 are on the slot.
Unfortunately with the VRMs based on the Comanche core (3565, 3566 and 3567) you can't selectively choose phases. I've verified this over email with an application engineer from IR as I had an application where I wanted to run phases 1,3,5 and turn off phases 2,4 and 6 on an IR3566B. It was physically impossible and I ended up having to sub-optimally disable 4-6 and leave 1-3 running.
The other thing is that you can't select the number of phases in real time. You can set the auto phase adjusting parameters and select the max number of phases, but you can't edit the max number of phases while the rail is active (IE, while GPU core voltage is applied). Essentially that means you can't edit that limit while the GPU is on.

Edit: Sorry, I did one too many looks of all the phase layouts out there. My own unit can't come soon enough. Based on the one by malventano, they could drop phase 6 from the PEG and leave it with 3 phases+memory on the 6 pin and 2 phases (+fan, likely) on the slot.

This is a corrected image for the phase/VRM layout:

This was verified via continuity testing by one of the users at overclock.net

I see your point about not being able to selectively control which phase gets turned off, however there are other options worth exploring.

The first is being able to adjust the Phase 1.. not sure if it supports negative values but if it does it could be used to balance the load, independent of which source this phase draws power from.

Also it is possible to adjust the loop offsets on the sensing side via software as well (see item IOUT Current Offset):

The controller has two loops loop1 for 4 rails and the loop2 for 2..

It looks like they can indeed modify this offset and this would support both increasing the current draw as well as lowering it. This would probably be their best bet.

 

[Silverforce11]

AMD will never learn. If they can churn out a new driver with these fixes why didn't they do it before the release? Now the RX 480 already has a bad rep just like 290 did and reviews are done. Any performance increase will not be seen by people looking at reviews. Plus a press release with a typo: 3%1. hat is that supposed to mean? 31%?

Could have been a lot worse. Like NV could have hired a few people to destroy their MB, set it on fire and post it on all the forums... that would have done a ton of damage! Looks like JHH is going easy on AMD.

 

[JDG1980]

Maybe AMD should hire The_Stilt? He seems to know more about their products than they do...

 

[MrTeal]

This is a corrected image for the phase/VRM layout:

This was verified via continuity testing by one of the users at overclock.net

I see your point about not being able to selectively control which phase gets turned off, however there are other options worth exploring.

The first is being able to adjust the Phase 1.. not sure if it supports negative values but if it does it could be used to balance the load, independent of which source this phase draws power from.



Also it is possible to adjust the loop offsets on the sensing side via software as well (see item IOUT Current Offset):



The controller has two loops loop1 for 4 rails and the loop2 for 2..

It looks like they can indeed modify this offset and this would support both increasing the current draw as well as lowering it. This would probably be their best bet.

See my edit; they are essentially adjusting the gain of the first three phases to force more current through them. The controller you linked is a little different though it's based on the same basic core. Rail 1 (or loop 1 if you prefer) has 6 phases that feed the core and rail 2 has two phases (1 active, apparently) that feeds the RAM.
There's going to be ripple consequences to doing it that way, but it's pretty likely they have sufficient margin that it's not an issue. For people like miners or single card users that don't particularly care about PCIe slot power draw, these changes might slightly negatively impact performance if you're trying to really minimize Vcore, but it should be minimal.

 

[sirmo]

Everyone's a critic. These types of bugs happen. It's really not a major bug.. and chances are people who designed the board designed it for the 150 TDP target.. before the final clocks and power limits were set.

Hardware revisions are a thing.. because humans make mistakes.

 

[sirmo]

See my edit; they are essentially adjusting the gain of the first three phases to force more current through them. The controller you linked is a little different though it's based on the same basic core. Rail 1 (or loop 1 if you prefer) has 6 phases that feed the core and rail 2 has two phases (1 active, apparently) that feeds the RAM.
There's going to be ripple consequences to doing it that way, but it's pretty likely they have sufficient margin that it's not an issue. For people like miners or single card users that don't particularly care about PCIe slot power draw, these changes might slightly negatively impact performance if you're trying to really minimize Vcore, but it should be minimal.

Gotcha, Thanks!

 

[MrTeal]

Gotcha, Thanks!

No problem. This has actually been really informative for me; I had no idea you could query PMBUS registers through the driver. I was going to solder on some leads to the I2C pins when I got my card in to talk directly to the VRM; this is a much more elegant (and less prone to crashes) solution.

 

[sirmo]

No problem. This has actually been really informative for me; I had no idea you could query PMBUS registers through the driver. I was going to solder on some leads to the I2C pins when I got my card in to talk directly to the VRM; this is a much more elegant (and less prone to crashes) solution.

Yeah I thought about it as well.. would be still useful to sniff the bus.. but I have more important stuff to work on.. like post on forums

Fun problem. Way overblown though.

 

[SPBHM]

The neighboring third pin on the top was reserved, but not actually assigned to anything. But now, in the latest standards, it’s generally used as an additional 12V pin, along with the other four, making it possible that a total of five pins are available for the 12V power supply. However, the allowed current was not changed to be compatible with older hardware.

so spec's[amps per pin] are [amps used divided by 4 pins] on the net. = over spec.
new cards use 5 pins the card are with in spec per pin amps lol
http://www.tomshardware.com/reviews...622.html?_ga=1.117291520.727157166.1467521787

sorry MR Teal quoted you by mistake

it would be interesting to know when this happened, when the 5th pin started to be used,


but I'm seeing from other posts some good news, if they deliver a driver fix in 2 days, this is the best case scenario I could think of :thumbsup: