The memory has to transfer information to the memory controller on the motherboard - it needs to transmit the data at the time that the memory controller expects to get it.
The memory controller producuces a 'clock' signal - a signal that changes from 'high' to 'low' on a regular basis, a complete 'high-low-high' transition forming a cycle. The importance of the clock signal is that it can be used to synchronise the operations of several devices - in this case it makes sure that the memory transfers its data at the time that the controller can deal with it.
When the controller wants some data from the memory it sends a command to the memory asking for it - it then waits a few clock cycles for the memory to find the data and begin transmission. The clock is important because it determines when exactly the controller will read the data. Although the memory may have found the data extremely quickly, the memory controller will only read the data on the low->high transition of the clock signal. This signal also tells the memory to find the next piece of data, so that on the next low->high transition, the memory controller can read some more data.
This is how SDR RAM works - one piece of data can be retrieved for every complete clock cycle.
DDR RAM is very similar, but is based on the fact that a clock signal has two 'edges', a low-high edge and a high-low edge. With DDR RAM two pieces of data can be transferred in each clock cycle. This allows two pieces of data to be transferred each clock cycle.