Technical question about DDR Sdram

[LordAlien]

Hi, what does it mean that DDR Sdram "carrie two data bits for each clock cycle"? I can't figure it out 'cos I'm not an engineer. Can anybody here explain me that or address me where this topic is well explained, even with pictures?
Maaaaaany thanx to you all.

 

[Jumpem]

The clock cycle looks like this:
__|--|__|--|__ , the mid-level dashes should be at the very top
..L..F..L..F..

The L = the leading edge of the clock cycle(the first upright).
The F = the falling edge of the clock cycle(the second upright).

Normal SDRAM only tranmits data on the leading edge.
DDR SDRAM sends and recievs data on both the leading and falling edges of the cycle, thus allowing two tasks per clock cycle.

Let me know if you are still confused, and I'll try to help.

 

[HellRaven]

I believe Jumpem has it right. Think of it like a ship in the sea when there are lots of waves. The ship starts into a wave and starts going up towards the top an it sends or receives. Then it hits the top (crest) and begins to go down towards the bottom (trough) and it sends or receives again. Thus it can send or receive twice per cycle (or twice per wave ). Regular Sdram can only do send or receive once during a cycle. Thus, with DDR you get better performance.

 

[LordAlien]

Well, I have hardly understood that....maybe 'cos I don't know how RAM works. We have a volatile memory made of transistors which are charged to temporarily store data and are cleared when the system is turned off. But RAM has to transmit bits to the CPU...so how does this work? We have surely a signal which is transmitted, indicating 0 or 1 - the bit - and this looks like this: -_-_ _- ...and so on. The upper score means 1 the underscore means 0....so I don't understand what one physically means for a cycle...Tha upper or under scores means the voltages used to identify the signals. But how do you physically identify a cycle?
Sorry for this confusion, but I'm a real beginner
Thanx a lot anyway.

A.Giulio - Rome, Italy

 

[NaughtyusMaximus]

Basically, instead of only sending one signal per each clock cycle (of the RAM), DDR is able to send two signals per clock cycle. It sends the information on the rise and the fall of the energy pluse instead of just the rise.

 

[Mark R]

The memory has to transfer information to the memory controller on the motherboard - it needs to transmit the data at the time that the memory controller expects to get it.

The memory controller producuces a 'clock' signal - a signal that changes from 'high' to 'low' on a regular basis, a complete 'high-low-high' transition forming a cycle. The importance of the clock signal is that it can be used to synchronise the operations of several devices - in this case it makes sure that the memory transfers its data at the time that the controller can deal with it.

When the controller wants some data from the memory it sends a command to the memory asking for it - it then waits a few clock cycles for the memory to find the data and begin transmission. The clock is important because it determines when exactly the controller will read the data. Although the memory may have found the data extremely quickly, the memory controller will only read the data on the low->high transition of the clock signal. This signal also tells the memory to find the next piece of data, so that on the next low->high transition, the memory controller can read some more data.

This is how SDR RAM works - one piece of data can be retrieved for every complete clock cycle.

DDR RAM is very similar, but is based on the fact that a clock signal has two 'edges', a low-high edge and a high-low edge. With DDR RAM two pieces of data can be transferred in each clock cycle. This allows two pieces of data to be transferred each clock cycle.