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[TechEye] GlobalFoundries to buy IBM Semi

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Also as far as I know FinFET is very good at reducing leakage.

Quite possible if they are within specs but a paper posted by Atenra point to high caracteristics dispersion of finfet in bulk process, it is highly likely that the mobile chips are cherry picked with the rest thrown in non mobile applications, i guess that the DT BT parts although decent perf/watt wise are some kind of waste recyclage.
 
This was the review made with the most efficient PSU , a 90W brick + pico PSU adaptator, for one, for two , wich chipset???.Theses are Socs and circuitry once called chipset is integrated in the Soc, the MB is reduced to a few meaningless circuits , VRMs and I/O, the two set ups use the same RAM, SSD or HD etc
Chipset was not the correct word, but you nonetheless have a non negligible amount of both digital and analog circuitry which consumption will vary a lot from a motherboard to another. I invite you to look at photographs of MB and you'll see it's far from being a single chip. All of this makes idle power consumption of the SoC mostly impossible to deduce from total power consumption. I bet different motherboards for the same chip will have idle power differences of a few watts.
 
Quite possible if they are within specs but a paper posted by Atenra point to high caracteristics dispersion of finfet in bulk process, it is highly likely that the mobile chips are cherry picked with the rest thrown in non mobile applications, i guess that the DT BT parts although decent perf/watt wise are some kind of waste recyclage.
That's a possibility. But I insist that we can't deduce idle power of the SoCs from the published reviews 🙂
 
That's a possibility. But I insist that we can't deduce idle power of the SoCs from the published reviews 🙂

The dutch site, hardware.info, has the test set up that allow the most precise evaluation within all sites.

Set up is :

150W brick + pico psu : expect 4W losses at most

SSD Corsair Vertex 4 128GB : 1.3W at iddle
http://www.hardware.fr/articles/860-25/consommation-efficacite-energetique.html

8GB RAM : about 1W when iddling

That s 6.3W , you can add 2W for the MB components to be cautious,
that s 8.3 , 1.3W is left for the 5350 and 8.5W for the J1800 to dissipate.

The BT MB :

gigabyte-j1900n-d3v.jpg



http://nl.hardware.info/reviews/533...ktopplatforms-intels-tegenhanger-bay-trail-dn
 
Once you forget the hear say and look at real numbers you ll see that GF 28nm is competitive with Intel s 22nm.

A 4C Kabini 2GHz has significantly lower iddle comsumption than a 2.4GHz 4C Baytrail and marginaly higher load comsumption but with better perfs overall.

http://nl.hardware.info/reviews/533...goedkope-desktopplatforms-stroomverbruik-idle

I was referring to 'big-core' CPUs, where Kaveri is not really competitive with Intel (there is no high end Kaveri that can compete with Core i7, for example). I haven't taken a look at Kabini yet (my bad). That said, I think it pretty widely accepted that GFL is N-2 to Intel.

If the "data king" aka IDC was still posting, he'd probably have some good info on the situation from an electrostatic perspective. Xtors/mm2 seems to be a bit ambiguous right now, though I'm pretty sure some professional Semicon publications has or will dig into that. I just don't feel like paying a grand a year (or whatever) for access to that kind of information.
 
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I've seen this same misunderstanding happen at least 3 times in the last month, it's ridiculous. Given how closely Apple work with ARM (first to ship 64-bit!), I refuse to believe that they didn't know that they were going to have a namespace clash.

'Namespace clash' - code in C++ often 🙂
 
I've seen this same misunderstanding happen at least 3 times in the last month, it's ridiculous. Given how closely Apple work with ARM (first to ship 64-bit!), I refuse to believe that they didn't know that they were going to have a namespace clash.
ARM succeeded in creating confusion with the architecture vs CPU names years ago. People are probably still confusing ARMv7 with ARM7 and vice versa, now add some Apple A7 and Cortex-A7 in the mix... 😱
 
EDIT: Apparently some confusion regarding Cortex A7 vs Apple A7? I thought Apple MRMT thought ARM.





Wish apple, ARM, and AMD would quit naming all their processors "A8 or A9 or A15"
 
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I think the slides you linked are from two different tests, or at least two test rigs. This is what Anand got in their Llano review:
Originally Posted by Anandtech
http://www.anandtech.com/show/4476/amd-a83850-review/9

Power Consumption Comparison
Intel Core i3-2105
Idle 51.7W
GPU Accelerated Video Transcoding 85W
3D Gaming (Metro 2033) 101W
CPU Load (x264 Encode) 87.6W
Even if we consider your 5600k numbers, we would still have a reasonable advantage for Sandy Bridge.

Consumption numbers alone are irrelevant,

From the AT Llano review
fbj7g5.jpg


Now lets see the performance in each of them,

Llano is using 25% more power but it is almost 65% faster than Core i3 2105 (HD3000). That only shows that Llano (32nm SOI) is more power efficient than 32nm SandyBridge.
39294.png


Now lets see x264, Llano consumes 40% more than Core i3 but it is also ~15% faster.
38881.png


Now lets see how much better Trinity(Bulldozer architecture) really is.
From AT A10-5800K review, not only A10-5800K is faster than Llano, it also consumes less and they are using the same 32nm SOI Process.
50400.png


50411.png
 
It's not roughly comparable, it's significantly worse! http://www.anandtech.com/bench/product/675?vs=399

But yes, I'm sure that a K10-derived core could have been much better if the bulk of AMD's CPU design resources weren't being spent on Bulldozer. Whether it would have been better than Bulldozer/Piledriver is another question, but unfortunately one that we can only consider in hypotheticals. It may well have been, it may not have been, we can't know.

Well, it's not significantly worse. In fact, there are some workloads that the old K10 is more than a match for Piledriver, beating it to the punch. You can't find a comparable case in Intel line up except for Netburst and you can't find the same in the rest of AMD line up.

Nah, I'd never go so far as to call Bulldozer/Piledriver a good architecture. In my view it is a passable design (inferior to Intel's), but hamstrung by the process node.

Well, it seems that we diverge only in the degree of loathing Bulldozer. Passable for you, extremely subpar for me. Maybe that's why you think SOI might help the designs, and I don't. To me Bulldozer and its derivatives are FUBAR'ed, end of history.
 
Well, it seems that we diverge only in the degree of loathing Bulldozer. Passable for you, extremely subpar for me. Maybe that's why you think SOI might help the designs, and I don't. To me Bulldozer and its derivatives are FUBAR'ed, end of history.

FD-SOI could have helped Kaveri by having the same clocks as Richland while consuming the same power as 28nm bulk. But that ship sailed a while ago. I never did find out why GFL didn't implement it (I'm guess it was not nearly as inexpensive to implement as SOITech presented it or the yields sucked).
 
FD-SOI could have helped Kaveri by having the same clocks as Richland while consuming the same power as 28nm bulk. But that ship sailed a while ago. I never did find out why GFL didn't implement it (I'm guess it was not nearly as inexpensive to implement as SOITech presented it or the yields sucked).

AMD stopped funding their custom node (probably SOI) at GLF when they amended the WSA in 2012, and this was well before the STM node was ready for prime.

I think the reason for that is that the big core faces a much deeper problem than not being able to raise the clock fast enough. AMD APU market share is being eaten by the nimble Intel 2C cores at the "upper" level, and by the 4C Kabini and Atom at the bottom. As SOI isn't enough to offset the N-1/N-2 node handicap they have from Intel, they have to focus on optimizing the product cost structure, not in making it faster, so ditching SOI makes sense. They make their market bracket a little narrower, but they improve the overall cost per unit of the remaining line up.
 
AMD stopped funding their custom node (probably SOI) at GLF when they amended the WSA in 2012, and this was well before the STM node was ready for prime.

Yeah, that was likely the main reason. AMD could't afford to pay for it and GFL wasn't willing to try and recoup the added cost over time. CPU wise, it likely would have added 15%+ to the performance (a nice jump in these days of single digit improvements), but it wouldn't have done anything for the GPU (since it's bandwidth limited). Yet again, it sucks being AMD.
 
Well, it seems that we diverge only in the degree of loathing Bulldozer. Passable for you, extremely subpar for me. Maybe that's why you think SOI might help the designs, and I don't. To me Bulldozer and its derivatives are FUBAR'ed, end of history.

Oh come on, you can at least agree that a better process node would make the APUs better. It's obviously not going to magically fix all of AMD's woes- there is plenty of things that still need fixing in their Steamroller architecture- but a node which reduced power consumption and increased clocks would at least make them a bit better. 😛

But yeah, we're basically on the same page, it seems. It's a matter of degrees.
 
Can someone explain the recent use of "N-1" and "N-2" on these forums ?
I hadn't noticed them being used in the past
 
Can someone explain the recent use of "N-1" and "N-2" on these forums ?
I hadn't noticed them being used in the past

Theses are terms coined out of clulessness, there s nothing like a two or even single node gap between the most advanced foundries, only a half node difference so the only relevant figure would be N-1/2.
 
Can someone explain the recent use of "N-1" and "N-2" on these forums ?
I hadn't noticed them being used in the past

"N" would be the state of the art technology- at the moment, that would be 22nm Intel. "N-1" means the equivalent of a previous generation, i.e. the equivalent of Intel's 32nm process. "N-2" would be the generation before that, so 45nm, and so on. Now obviously 28nm GloFo is superior to Intel's 45nm process, so N-2 is a rather big exaggeration, but they are certainly behind. Probably somewhere around N-1.
 
Probably somewhere around N-1.

Browse through the previous page and do a comparison between AMDs Kabini and Intel s BT efficency and you ll see that there s hardly a half node between GF s 28nm and Intel s 22nm when looking at the raw numbers in terms of watts and performance.
 
Oh come on, you can at least agree that a better process node would make the APUs better. It's obviously not going to magically fix all of AMD's woes- there is plenty of things that still need fixing in their Steamroller architecture- but a node which reduced power consumption and increased clocks would at least make them a bit better. 😛

Ok, I'll give you that 😛
 
Quite possible if they are within specs but a paper posted by Atenra point to high caracteristics dispersion of finfet in bulk process, it is highly likely that the mobile chips are cherry picked with the rest thrown in non mobile applications, i guess that the DT BT parts although decent perf/watt wise are some kind of waste recyclage.

FinFETs are specifically made to reduce leakage at the gate, to make off more off.
 
2020 is very early; I don't expect CNTs to arrive before Intel's 5nm node, which we'll see in 2020 at the earliest, possibly even later.
 
Nope the foundries are going to be "sold" but may stay under IBMs names for legal/tax reasons. GF will run them and shut down 1 before the end of 2015 and the other will be shut down soon as well.

Official notices are going out this week for the IBM people will start working for GF's and that that entails.

I have a friend at IBM and he said the news will be coming out this week. If you own a house in the fish kill area, sell soon.
 
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