<< well to be specific, if you want to store a specific piece of data, say the number -5, you need to have MULTIPLE bits to show that the number is -, and that it is 5. if the number was just 5, it would be 101 in binary. if you're in 16 bit mode, and you wanted say a -5, then you have 1111111111111011 to represent it. >>
Technically speaking, in a 16-bit computer, 5 is 0000000000000101 and -5 is 1111111111111011, so there's no real advantage to abandoning the 2's complement approach. Integer values takes up space up to the maximum value of the allocated entry. So a 64-bit number - either positive or negative - will always take up 64 bits - whether or not the value is merely "1" and you are 'wasting' 63 of them. I know you know this, Soccer, I'm just pointing out that it's not fair to say this is a wate.
You could simply have a pos/neg bit separate to the number - which would be 101-0 for "5" and 101-1 for "-5". Everything would look better on paper, but you'd pay a hefty price in hardware (and chip cost) by having to implement subtractors in addition to adders. Besides, like I said, this doesn't save you anything.
Intel Flash memory (and maybe a few other companies, but I know Intel for certain) uses multiple levels to encode more than one bit of data into a memory cell. There are noise concerns with doing it in a CPU, and I don't see it happening any time soon - especially not with voltage levels continuing to drop in these submicron days. I don't think that I can agree with you, Soccerman, that it's destined to be the format of the future. In specific devices like Flash, and maybe DRAM, but I definitely don't think it would work in a CPU - not without a huge amount of engineering effort, anyway, and this effort almost certainly wouldn't equal the gain.
Engineers use binary because it's easy. CMOS is binary, it's either on or off and everyone designs everything to switch to rails. At best you might be able to convert the cache arrays on chip to multi-level but this would be at a cost of latency. Probably a substantial latency cost (as a percentage of total latency) if you did the L1 array of a chip, a lesser cost if you did the L2. But it wouldn't be pretty to design or debug... and I wouldn't want to guess what an alpha particle would do to the values - since you would now be corrupting two bits instead of just 1, so ECC would be harder to implement.
Multi-level data storage may be our destiny, but I don't see it in CPUs or DRAMs any time soon. Still, it's a good point to bring up since it may offer one way around the superparamegnetism limit.
As far as the actual subject of the thread, first off there's enough money involved that we will switch to something else when we hit this limit. There might be a capactity plateau (where, for a few years, sizes are constant while everyone works on spin rate or something else), but it's definitely not "all over". Besides, these are TeraByte harddisks we are talking about... that's still a long way in the future.
Edit: I must have been asleep when I first wrote this. There were a bunch of grammar and spelling errors. Anyway, I think I've cleaned it up now.