Originally posted by: krcat1
The new cores are San Diego and Venice (FX and 64) both are to have SSE3 support and other improvements. They will use socket 939.
Originally posted by: bersl2
All indications say that it (and the improved memory controller, and the strained silicon) will be on the E0 stepping, shipping in volume 2005Q3.
Or something like that.
Originally posted by: Rich85
i believe sse3 will be on the new dual cores, although i might be wrong .. http://www.dvhardware.net/article3247.html
Originally posted by: zakee00
no need for SSE3, its all marketing.
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2350
Originally posted by: Googer
Originally posted by: bersl2
All indications say that it (and the improved memory controller, and the strained silicon) will be on the E0 stepping, shipping in volume 2005Q3.
Or something like that.
E0 is Intel, if i am not mistaken.